Metehan Dundar
a8fca2afdb
Format code with black and fix flake8 linting issues
...
- Applied black formatting with line length 99
- Fixed flake8 linting issues (E265 block comments)
- All 115 tests still pass after formatting
- Code style is now consistent across the codebase
Changes:
- osaca/parser/base_parser.py: improved line breaks and comment formatting
- osaca/osaca.py: added missing blank line
- osaca/db_interface.py: reformatted long lines and comments
- osaca/parser/parser_RISCV.py: extensive formatting improvements
- osaca/semantics/kernel_dg.py: improved formatting and readability
- osaca/semantics/hw_model.py: fixed shebang and formatting
- osaca/semantics/marker_utils.py: removed TODO comment and formatting
2025-07-11 22:28:29 +02:00
Metehan Dundar
ebf76caa18
Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames
...
- Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support
- Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.)
- Renamed example files from rv6 to rv64 for consistency
- Updated related configuration and test files
- All 115 tests pass successfully
2025-07-11 18:15:51 +02:00
Metehan Dundar
61b52dbf28
RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests
...
- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
2025-06-30 00:28:52 +02:00
Metehan Dundar
480c0dcac0
Merge branch 'master' into dev/risc-v
2025-05-08 12:23:22 +02:00
Robin Leroy
da2ce51446
white on blue
2025-03-27 23:12:25 +01:00
Robin Leroy
4526baa6ae
Less clever and more useful colouring
2025-03-27 23:12:19 +01:00
Robin Leroy
9040757e91
Improve dependency graph colouring
2025-03-27 23:11:57 +01:00
Robin Leroy
638d938325
Mark backward edges as backward so the graph is ordered like the code
2025-03-27 23:11:46 +01:00
Robin Leroy
a4c6d84b0c
Don’t spam filled until dot breaks
2025-03-27 23:11:35 +01:00
Robin Leroy
034d192c57
Don’t run out of colours
2025-03-27 23:11:21 +01:00
pleroy
ed263f696a
Moar colors.
2025-03-27 23:11:13 +01:00
Metehan Dundar
d782f06e84
Add RISC-V support and update version to 0.6.2
2025-03-21 17:16:39 +01:00
Metehan Dundar
653c27135d
Add initial support for RISC-V architecture and update relevant files
2025-03-11 05:10:03 +01:00
JanLJL
ffb5f0eb55
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
bcecabd911
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
63f56e50b4
black formatting
2025-03-05 10:20:47 +01:00
JanLJL
fb7f1a289d
flake8 formatting
2025-03-05 10:19:10 +01:00
JanLJL
1be2f320b9
add default syntax for get_parser for compatibility with kerncraft
2025-03-04 17:44:02 +01:00
JanLJL
dbbbe743ac
get_marker() needed for kerncraft
2025-03-03 18:26:33 +01:00
pleroy
b4d342266d
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
8f84368db9
initial support ZEN 4
2024-08-30 17:41:45 +02:00
JanLJL
2fce0520d7
fixed bug in read-out of default store TP
2024-08-19 14:37:20 +02:00
JanLJL
b11a1c7cf7
Merge branch 'master' into feat/spr
2024-05-02 21:19:10 +02:00
JanLJL
aeecac3b5f
Black formatting
2024-05-02 17:04:56 +02:00
JanLJL
a790ab7e79
Flake8 formatting
2024-05-02 17:00:12 +02:00
JanLJL
17e9b80282
formattign
2024-05-02 16:30:11 +02:00
JanLJL
2e29f0b4e1
moved get_full_instruction_name() from HardwareModel to DBInterface
2024-05-02 16:25:41 +02:00
stefandesouza
ae2fcfe8bb
added prefetch operand
2024-03-18 22:29:39 +01:00
JanLJL
46a67211bc
initial support for SPR
2024-03-06 00:52:06 +01:00
stefandesouza
e253638cb7
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
fa56fd0183
Uncommented tests
2024-03-05 00:19:29 +01:00
stefandesouza
4ec3788f58
Dump now converts classes to dicts
2024-03-05 00:18:45 +01:00
JanLJL
76c1692f5b
initial support Neoverse V2
2024-03-04 20:45:48 +01:00
stefandesouza
62c21a7f31
Port pressure returned in tuple with Memory Operand
2024-03-04 20:00:43 +01:00
stefandesouza
d944c82d33
Immediate operand attribute name changes
2024-02-28 13:01:37 +01:00
stefandesouza
9cd841cd08
Added updated files
2024-02-27 14:47:55 +01:00
stefandesouza
0474148d7b
Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples
2024-02-24 21:03:15 +01:00
stefandesouza
eaeb408e87
Inlined conversion of LD/ST memory operands
2024-02-24 12:45:59 +01:00
stefandesouza
85677d1b0c
Flags into operand class
2024-02-24 12:11:52 +01:00
stefandesouza
33ad20dc3a
More formatting
2024-01-10 13:26:50 +01:00
stefandesouza
b8e88f9319
Merge remote-tracking branch 'origin/master' into InstrucForm
2023-12-16 12:14:36 +01:00
JanLJL
b2f49bdf6a
added M1 arch
2023-12-12 18:33:24 +01:00
JanLJL
b7ff0b1461
bugfixes for SP reg and ccodes
2023-12-12 18:32:43 +01:00
stefandesouza
405a1d2857
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
47a44c9865
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
1885ce6ddb
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
e77dfb4eb3
Fixed issue with throughput assignment
2023-10-30 19:32:05 +01:00
