Metehan Dundar
a8fca2afdb
Format code with black and fix flake8 linting issues
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- Applied black formatting with line length 99
- Fixed flake8 linting issues (E265 block comments)
- All 115 tests still pass after formatting
- Code style is now consistent across the codebase
Changes:
- osaca/parser/base_parser.py: improved line breaks and comment formatting
- osaca/osaca.py: added missing blank line
- osaca/db_interface.py: reformatted long lines and comments
- osaca/parser/parser_RISCV.py: extensive formatting improvements
- osaca/semantics/kernel_dg.py: improved formatting and readability
- osaca/semantics/hw_model.py: fixed shebang and formatting
- osaca/semantics/marker_utils.py: removed TODO comment and formatting
2025-07-11 22:28:29 +02:00
Metehan Dundar
ebf76caa18
Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames
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- Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support
- Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.)
- Renamed example files from rv6 to rv64 for consistency
- Updated related configuration and test files
- All 115 tests pass successfully
2025-07-11 18:15:51 +02:00
Metehan Dundar
61b52dbf28
RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests
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- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
2025-06-30 00:28:52 +02:00
Metehan Dundar
480c0dcac0
Merge branch 'master' into dev/risc-v
2025-05-08 12:23:22 +02:00
Metehan Dundar
aa3753d024
Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files
2025-05-08 11:57:06 +02:00
Jan
2c4a545f3b
Merge pull request #116 from eggrobin/graph-colouring
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Improvements to graph layout and colouring
2025-03-31 11:38:23 +02:00
Jan
25bcf59789
Merge pull request #115 from pleroy/Comisd
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Support for arithmetic shift and comparison instructions for x86
2025-03-31 11:18:09 +02:00
Robin Leroy
da2ce51446
white on blue
2025-03-27 23:12:25 +01:00
Robin Leroy
4526baa6ae
Less clever and more useful colouring
2025-03-27 23:12:19 +01:00
Robin Leroy
9040757e91
Improve dependency graph colouring
2025-03-27 23:11:57 +01:00
Robin Leroy
638d938325
Mark backward edges as backward so the graph is ordered like the code
2025-03-27 23:11:46 +01:00
Robin Leroy
a4c6d84b0c
Don’t spam filled until dot breaks
2025-03-27 23:11:35 +01:00
Robin Leroy
034d192c57
Don’t run out of colours
2025-03-27 23:11:21 +01:00
pleroy
ed263f696a
Moar colors.
2025-03-27 23:11:13 +01:00
pleroy
939089030b
Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.
2025-03-27 22:47:32 +01:00
Robin Leroy
d2b8b7771f
ucomisd is like comisd
2025-03-27 22:46:48 +01:00
pleroy
ea59056f94
Define comisd sources.
2025-03-27 22:46:38 +01:00
Jan
ce0f78e441
Merge pull request #114 from eggrobin/setmeow-jmeow
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Add the x86 SET* and J* instructions
2025-03-26 09:05:23 +01:00
Metehan Dundar
d782f06e84
Add RISC-V support and update version to 0.6.2
2025-03-21 17:16:39 +01:00
Robin Leroy
122f8a674b
Configure the dependencies of the jmeow instructions on flags
2025-03-20 22:30:00 +01:00
Robin Leroy
94f32c51a7
Add the setmeow instructions
2025-03-20 22:29:51 +01:00
JanLJL
734979521b
use pypi version of kerncraft for GH Actions
2025-03-19 14:36:49 +01:00
JanLJL
1627f0e49d
version bump
2025-03-17 10:28:06 +01:00
JanLJL
68252c86b9
remove AT&T limitation
2025-03-17 10:27:41 +01:00
Jan
d4d84fa49e
add syntax flag in README
2025-03-17 10:26:50 +01:00
Jan
2b838b7bdd
Merge pull request #112 from pleroy/Intel
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Add support for the Intel syntax produced by MSVC and ICC
2025-03-17 10:20:40 +01:00
JanLJL
31f5912af6
take +- operator of offset/index in mem-addr into account
2025-03-14 18:46:12 +01:00
Metehan Dundar
850f7edc6b
RISCV.yml file has been updated.
2025-03-13 09:54:06 +01:00
pleroy
732dd95810
Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle.
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I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.
2025-03-12 22:26:38 +01:00
pleroy
f846f0ed7d
Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/
2025-03-12 00:35:01 +01:00
pleroy
e3910056cf
Revert d772522400 and fix a failure in tests.test_cli.TestCLI.test_without_arch while preserving the possibility to try more archs than the detected one.
2025-03-11 23:34:36 +01:00
Metehan Dundar
a75098c9f5
Add RISCV parser to test suite
2025-03-11 11:42:15 +01:00
Metehan Dundar
653c27135d
Add initial support for RISC-V architecture and update relevant files
2025-03-11 05:10:03 +01:00
JanLJL
ffb5f0eb55
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
bcecabd911
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
022bd2997d
add setuptools to Install
2025-03-05 13:19:09 +01:00
JanLJL
bec925d5aa
specify commit for kerncraft
2025-03-05 12:54:55 +01:00
JanLJL
461bf0306f
undo unnecessary install
2025-03-05 11:01:47 +01:00
JanLJL
585e2d6177
use local osaca version
2025-03-05 11:00:08 +01:00
JanLJL
b7e5df0a08
more black formatting
2025-03-05 10:40:18 +01:00
JanLJL
799acd5c20
install kerncraft from git repo
2025-03-05 10:38:39 +01:00
JanLJL
63f56e50b4
black formatting
2025-03-05 10:20:47 +01:00
JanLJL
fb7f1a289d
flake8 formatting
2025-03-05 10:19:10 +01:00
JanLJL
a4939d1873
renamed .asm files to .s for consistency
2025-03-05 09:36:07 +01:00
JanLJL
4e6d37aa9f
bugfixes
2025-03-04 17:46:37 +01:00
JanLJL
1c2e0f3921
chmod +x
2025-03-04 17:46:23 +01:00
JanLJL
3de6097a06
add test case for specific syntax parameter in get_asm_parser()
2025-03-04 17:45:19 +01:00
JanLJL
b6c3c924c6
remove dependency on MachineModel
2025-03-04 17:44:27 +01:00
JanLJL
1be2f320b9
add default syntax for get_parser for compatibility with kerncraft
2025-03-04 17:44:02 +01:00
JanLJL
379e422290
remove dependency on MachineModel
2025-03-04 17:42:52 +01:00
