Commit Graph

11 Commits

Author SHA1 Message Date
pleroy
b4d342266d Add support for the Intel syntax supported by MSVC and ICC 2025-02-02 14:02:16 +01:00
JanLJL
61485e2fdc formatting 2024-09-05 10:44:23 +02:00
JanLJL
8d7e68d6aa bugfix 2024-09-05 08:42:53 +02:00
JanLJL
5902ef1c75 fixed formatting 2024-09-04 13:10:58 +02:00
JanLJL
f098e8628d updated for newer uarchs 2024-09-04 09:52:32 +02:00
JanLJL
19d3a27355 added SVE reg width output in main func 2024-09-03 14:27:28 +02:00
stefandesouza
37ca6670c7 pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also 2023-12-02 16:56:43 +01:00
JanLJL
1b40c10a1f applied flake8 and black rules 2021-08-26 16:58:19 +02:00
Julian Hammer
781b8b6b89 improved register range and list support on AArch64 2021-04-23 13:12:18 +02:00
Julian Hammer
c54685ee2c readme added to validation folder 2021-04-15 14:45:23 +02:00
Julian
04836cf3f9 Validation (#71)
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.

build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.

For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz

The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb

Quite a few changes on OSACA included:

Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00