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Author	SHA1	Message	Date
JanLJL	1359cc92ba	adjusted non-instruction_form fields	2021-11-29 15:17:38 +01:00
Qingcai Jiang	de0982226b	add some instructions with ibench	2021-11-17 17:49:05 +08:00
Qingcai Jiang	2d38cac9a1	simple implement for TSV110	2021-11-06 16:04:16 +08:00
JanLJL	6f3b36e58c	version bump	2021-11-04 14:56:23 +01:00
JanLJL	f901b481da	black formatting	2021-11-04 12:11:15 +01:00
JanLJL	1d6e0d5a42	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2021-11-04 12:09:57 +01:00
JanLJL	d84a6399dd	Closes #78, closes #79; added unary/binary logical operators	2021-11-04 12:09:44 +01:00
JanLJL	c659aebe4b	add latency of last instruction in CP	2021-11-04 11:58:40 +01:00
JanLJL	f801950ffb	better output formatting	2021-11-04 11:55:48 +01:00
Jan	2995f1873d	Merge pull request #60 from RRZE-HPC/a72 ... Add support for ARM Cortex-A72	2021-10-14 18:10:36 +02:00
JanLJL	c36fab40cb	added Cortex A72 in README	2021-10-14 17:10:08 +02:00
JanLJL	4e967380d6	formatted	2021-10-14 10:59:55 +02:00
JanLJL	3789e065c6	formatted	2021-10-14 10:53:34 +02:00
JanLJL	3971e9e853	Merge branch 'master' into a72	2021-10-14 10:37:05 +02:00
JanLJL	3b20246fc3	unified format	2021-10-14 09:23:35 +02:00
JanLJL	8c94378437	version bump	2021-10-07 17:10:17 +02:00
JanLJL	bc7761007c	fixed formatting with correct line length	2021-10-04 15:00:17 +02:00
JanLJL	314feb4104	black formatting	2021-10-04 14:33:28 +02:00
JanLJL	217fcff664	black conformity	2021-09-30 15:53:56 +02:00
JanLJL	f1f119f5a0	added instructions for BHIVE	2021-09-29 17:26:44 +02:00
JanLJL	3404d72dc5	enhanced parser	2021-09-29 17:26:27 +02:00
Jan	b2e914db4a	added lint configs	2021-08-27 08:14:50 +02:00
JanLJL	1b40c10a1f	applied flake8 and black rules	2021-08-26 16:58:19 +02:00
JanLJL	db30a4e36c	fixed wrong uops info import with masking of some gather/scatter	2021-08-26 11:05:33 +02:00
JanLJL	44f3c0376e	version bump	2021-07-21 02:41:05 +02:00
JanLJL	a721d0941d	added more load instrs	2021-07-21 02:34:31 +02:00
JanLJL	2d17a48604	updated a few DB entries	2021-06-02 16:37:18 +02:00
JanLJL	98de6f2a92	version bump	2021-06-01 00:13:38 +02:00
JanLJL	ec771dbe91	fixed parsing of reg ranges and lists	2021-06-01 00:10:05 +02:00
JanLJL	8cc36e6691	version bump	2021-05-10 12:56:35 +02:00
JanLJL	5038ce7a15	changed immediate type from str to int	2021-05-10 01:12:30 +02:00
JanLJL	261ad22ccb	version bump	2021-05-05 11:16:43 +02:00
JanLJL	8e09927178	added tests for timeout in LCD analyis	2021-05-02 22:48:22 +02:00
JanLJL	e988251c49	fixed bug in case of no uarch in CLI	2021-05-02 22:39:07 +02:00
JanLJL	30d6f4d737	fix #73	2021-05-02 22:22:30 +02:00
Julian Hammer	5ac87b3475	added missing testfile for sve instructions	2021-05-02 21:44:17 +02:00
Julian Hammer	31e35d8815	addd LD2 and ST2 instructions to a64fx	2021-04-23 13:33:32 +02:00
Julian Hammer	c4163dd930	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2021-04-23 13:18:23 +02:00
Julian Hammer	781b8b6b89	improved register range and list support on AArch64	2021-04-23 13:12:18 +02:00
JanLJL	129052a84a	fixed incompatibilty to py3.6	2021-04-20 13:59:56 +02:00
JanLJL	c1234e2d45	set min requirement to py3.6	2021-04-20 13:59:32 +02:00
JanLJL	08b29e93a0	added wheel to pypi publishing	2021-04-19 11:33:29 +02:00
JanLJL	5ef7aa3466	fixed duplicate hyperlink tags	2021-04-19 10:58:11 +02:00
JanLJL	730132881d	added no timeout option	2021-04-19 10:57:51 +02:00
JanLJL	e93672d5ff	version bump	2021-04-19 10:14:26 +02:00
JanLJL	af947c54f5	Merge branch 'master' of https://github.com/RRZE-HPC/OSACA	2021-04-19 00:34:32 +02:00
JanLJL	b2af6a61c6	bugfixed CLX as uarch flag	2021-04-19 00:34:21 +02:00
Jan	e139833eab	added lcd-timeout flag, citations and updated credits	2021-04-19 00:27:24 +02:00
JanLJL	6208536863	added CLX as synonym for CSX uarch	2021-04-19 00:05:53 +02:00
JanLJL	5b95f1f909	enhanced LCD analysis by making it parallel and added timeout flag	2021-04-19 00:04:03 +02:00