7 Commits

Author	SHA1	Message	Date
Metehan Dundar	1ceac6e9f3	Refactor: RISC-V parser, code formatting, and flake8 compliance ... - Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand. - Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility. - Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase. - Improved docstrings and split long lines for better readability. - Fixed test failures related to ImmediateOperand instantiation and attribute errors. - Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64. - Updated .gitignore and documentation as needed. - Renamed example files for consistency (rv6 -> rv64).	2025-07-04 23:21:06 +02:00
JanLJL	31f5912af6	take +- operator of offset/index in mem-addr into account	2025-03-14 18:46:12 +01:00
pleroy	732dd95810	Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. ... I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.	2025-03-12 22:26:38 +01:00
JanLJL	63f56e50b4	black formatting	2025-03-05 10:20:47 +01:00
JanLJL	fb7f1a289d	flake8 formatting	2025-03-05 10:19:10 +01:00
JanLJL	379e422290	remove dependency on MachineModel	2025-03-04 17:42:52 +01:00
pleroy	b4d342266d	Add support for the Intel syntax supported by MSVC and ICC	2025-02-02 14:02:16 +01:00