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c3e59edb2ac21fc86f0200d1c1b89261f2dc62cd
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922 Commits

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Author SHA1 Message Date
stefandesouza
c3e59edb2a Module imports 2023-08-20 13:37:57 +02:00
stefandesouza
17ef6582d1 InstrucForm class usage in AArch parser 2023-08-20 13:35:11 +02:00
stefandesouza
4a382193a5 Separate operand files with inheritance, str and repr classes 2023-08-20 12:10:07 +02:00
stefandesouza
37e7d5bbd5 Merge remote-tracking branch 'origin/master' into InstrucForm 
merge
 2023-08-20 11:39:20 +02:00
stefandesouza
1d5ff61890 Added seperate operand class files 2023-08-20 11:38:56 +02:00
JanLJL
f7c6c5812c version bump 2023-08-16 00:58:23 +02:00
Jan
d9a7ee8c06 Update modules used in GH actions 2023-08-15 14:55:10 +02:00
Jan
bd8d72bd6b Added --yaml-out flag 2023-08-15 14:33:22 +02:00
Jan
f51c122dca Merge pull request #96 from stephenswat/feat/yaml_output 
Add support for structured YAML output
 2023-08-15 14:31:31 +02:00
JanLJL
c88b637e5c added tests for dict output of analysis 2023-08-15 14:01:15 +02:00
JanLJL
29c00462e2 enhanced YAML output to include all kernel objects and no ruamel.yaml-specific data types 2023-08-15 14:01:11 +02:00
JanLJL
fd300cf687 Merge branch 'master' into pr96 2023-08-15 08:59:22 +02:00
Jan
15969ef82a Merge pull request #95 from stephenswat/feat/zen3_imul 
Add IMUL instruction for Zen 3 architectures
 2023-08-15 08:57:59 +02:00
Stephen Nicholas Swatman
8615c33df6 Add support for structured YAML output 
This commit adds a new `--yaml-out` flag to OSACA which allows the user
to dump the results of an analysis to a YAML file, allowing them to
analyse the file more easily. I have tried to make the output as
comprehensive as possible.
 2023-08-12 19:43:43 +02:00
Stephen Nicholas Swatman
2203517e8e Add IMUL instruction for Zen 3 architectures 
This commit adds data on the IMUL (r, r) instruction on the AMD Zen 3
microarchitecture.
 2023-08-12 19:40:44 +02:00
stefan.desouza@outlook.com
b70916e4f8 Classes for OperandForm and Operand types 2023-08-07 15:01:48 +02:00
stefan.desouza@outlook.com
49f6c6a881 Added DirectiveClass with comment iterator 2023-08-06 17:42:42 +02:00
stefan.desouza@outlook.com
981c22b9fb Added InstructionForm class 2023-08-06 17:13:42 +02:00
JanLJL
87ce1d2b29 version bump 2023-08-02 11:26:45 +02:00
JanLJL
b43773f1b8 added new instructions 2023-08-02 11:04:56 +02:00
JanLJL
54a030c3e5 changed TP/LT for reg renaming moves 2023-08-02 11:03:31 +02:00
Jan
57fba427b2 Update issue templates 2023-07-18 17:24:10 +02:00
JanLJL
7b83ef7b50 fixed UnboundLocalError if tp assignment loop is not executed 2023-07-17 14:52:22 +02:00
JanLJL
080eb8c7f0 fixes #93 2023-07-17 14:22:05 +02:00
JanLJL
73fe466235 added shift instructions 2023-07-05 16:42:34 +02:00
JanLJL
d4f6314928 fixed read out of store TP from DB 2023-06-20 21:20:41 +02:00
JanLJL
1d73221e62 added reg specific store TP 2023-06-20 21:17:37 +02:00
JanLJL
f233b00905 adjusted scraper due to new felixcloutier table layout 2023-06-20 21:16:40 +02:00
JanLJL
3fcba304b2 version dump 2023-03-24 17:42:03 +01:00
Jan
2723791b8b fixed nested list 2023-03-24 17:08:59 +01:00
JanLJL
79c6cb6d0a added p-indexing latency values for Arm architectures 2023-03-24 17:05:45 +01:00
JanLJL
12ee82e8da updated requirements 2023-03-24 17:05:29 +01:00
JanLJL
8b923f0d6c updated README with new parameter info 2023-03-24 16:39:58 +01:00
Jan
b9f1b8884f Merge pull request #92 from dgazzoni/aarch64-conditions-codes 
Support for flags and conditional ops on AArch64
 2023-03-21 18:08:54 +00:00
JanLJL
261039e51e black-compliant formatting 2023-03-14 18:22:27 +01:00
JanLJL
1f010ecf7e add missing instruction for test 2023-03-14 17:51:20 +01:00
JanLJL
97756faa04 Merge branch 'master' into pr-armcc 2023-03-14 17:50:48 +01:00
JanLJL
71b425c1de added support for optional condition flag dependency analysis 2023-03-14 17:00:49 +01:00
JanLJL
7c6de89f30 more instructions 2023-03-14 17:00:23 +01:00
JanLJL
0985e81b23 added more dependency analysis for post/pre indexing and condition flags 2023-03-14 17:00:02 +01:00
JanLJL
1b261912e0 renamed condition code attrib, fixed incorrect src/dst, and added more conditional instructions 2023-03-14 16:57:34 +01:00
JanLJL
23139d4d5b bugfix, resolved #90 2023-03-07 17:05:31 +01:00
JanLJL
27828ec5b4 added instruction 2023-03-07 17:04:32 +01:00
JanLJL
2cc338d107 formatting according to black 2023-03-03 15:24:18 +01:00
JanLJL
72f69fa707 added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes 2023-03-03 15:11:40 +01:00
JanLJL
c1373fe44c enabled indexing without shape and lane for vector regs 2023-03-03 14:41:48 +01:00
JanLJL
1938e889d3 added another instruction 2023-03-03 14:39:28 +01:00
JanLJL
37c8598b36 resolve #81 2023-03-02 15:50:13 +01:00
Décio Luiz Gazzoni Filho
b434e30ec1 Support for flags and conditional ops on AArch64 2023-02-19 22:08:42 -03:00
JanLJL
d8f386ccdc version bump 2023-02-15 19:03:11 +01:00