Lerking/OSACA
1
0
Fork 0
mirror of https://github.com/RRZE-HPC/OSACA.git synced 2025-12-16 00:50:06 +01:00
Code Issues Packages Projects Releases Wiki Activity
917 Commits 2 Branches 44 Tags
dc250bcedcff15a0fb090eff3abd398696c1f5fa
Commit Graph

917 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
JanLJL
dc250bcedc initial commit of M1 model (not complete) 2023-09-28 10:04:15 +02:00
JanLJL
74478034f7 Merge branch 'master' of github.com:RRZE-HPC/osaca 2023-09-13 09:49:28 +02:00
JanLJL
8cc408a307 version bump v0.5.2 2023-08-16 00:58:23 +02:00
Jan
6d275a1207 Update modules used in GH actions 2023-08-15 14:55:10 +02:00
Jan
c2ee276609 Added --yaml-out flag 2023-08-15 14:33:22 +02:00
Jan
03a9caf0eb Merge pull request #96 from stephenswat/feat/yaml_output 
Add support for structured YAML output
 2023-08-15 14:31:31 +02:00
JanLJL
f856c578bf added tests for dict output of analysis 2023-08-15 14:01:15 +02:00
JanLJL
ab10febe74 enhanced YAML output to include all kernel objects and no ruamel.yaml-specific data types 2023-08-15 14:01:11 +02:00
JanLJL
b50bc9ba1f Merge branch 'master' into pr96 2023-08-15 08:59:22 +02:00
Jan
01cc93f56c Merge pull request #95 from stephenswat/feat/zen3_imul 
Add IMUL instruction for Zen 3 architectures
 2023-08-15 08:57:59 +02:00
Stephen Nicholas Swatman
e1ce402133 Add support for structured YAML output 
This commit adds a new `--yaml-out` flag to OSACA which allows the user
to dump the results of an analysis to a YAML file, allowing them to
analyse the file more easily. I have tried to make the output as
comprehensive as possible.
 2023-08-12 19:43:43 +02:00
Stephen Nicholas Swatman
7cd380e7b8 Add IMUL instruction for Zen 3 architectures 
This commit adds data on the IMUL (r, r) instruction on the AMD Zen 3
microarchitecture.
 2023-08-12 19:40:44 +02:00
JanLJL
c599ce4967 fixed wrong LEA DB entry 2023-08-03 11:13:23 +02:00
JanLJL
e476893dec version bump v0.5.1 2023-08-02 11:26:45 +02:00
JanLJL
c090d24edf added new instructions 2023-08-02 11:04:56 +02:00
JanLJL
9f9471ee4e changed TP/LT for reg renaming moves 2023-08-02 11:03:31 +02:00
Jan
870074b7ab Update issue templates 2023-07-18 17:24:10 +02:00
JanLJL
1125e4c5d9 fixed UnboundLocalError if tp assignment loop is not executed 2023-07-17 14:52:22 +02:00
JanLJL
88a1efe633 fixes #93 2023-07-17 14:22:05 +02:00
JanLJL
a0d8895d38 added shift instructions 2023-07-05 16:42:34 +02:00
JanLJL
c6ed492db3 fixed read out of store TP from DB 2023-06-20 21:20:41 +02:00
JanLJL
1ac20073ab added reg specific store TP 2023-06-20 21:17:37 +02:00
JanLJL
0a2d1f866d adjusted scraper due to new felixcloutier table layout 2023-06-20 21:16:40 +02:00
JanLJL
d46574db1f version dump v0.5.0 2023-03-24 17:42:03 +01:00
Jan
8e6289af1a fixed nested list 2023-03-24 17:08:59 +01:00
JanLJL
2a43676097 added p-indexing latency values for Arm architectures 2023-03-24 17:05:45 +01:00
JanLJL
c354306b3b updated requirements 2023-03-24 17:05:29 +01:00
JanLJL
9e3ab49065 updated README with new parameter info 2023-03-24 16:39:58 +01:00
Jan
475823d4dc Merge pull request #92 from dgazzoni/aarch64-conditions-codes 
Support for flags and conditional ops on AArch64
 2023-03-21 18:08:54 +00:00
JanLJL
54644ffb09 black-compliant formatting 2023-03-14 18:22:27 +01:00
JanLJL
af3b1fe3e8 add missing instruction for test 2023-03-14 17:51:20 +01:00
JanLJL
0b93766bdd Merge branch 'master' into pr-armcc 2023-03-14 17:50:48 +01:00
JanLJL
eab6907c82 added support for optional condition flag dependency analysis 2023-03-14 17:00:49 +01:00
JanLJL
27eb8f62b6 more instructions 2023-03-14 17:00:23 +01:00
JanLJL
d1201ace11 added more dependency analysis for post/pre indexing and condition flags 2023-03-14 17:00:02 +01:00
JanLJL
d6569a0f23 renamed condition code attrib, fixed incorrect src/dst, and added more conditional instructions 2023-03-14 16:57:34 +01:00
JanLJL
7e6eb7ce58 bugfix, resolved #90 2023-03-07 17:05:31 +01:00
JanLJL
10d4c4b87e added instruction 2023-03-07 17:04:32 +01:00
JanLJL
f06f767c34 formatting according to black 2023-03-03 15:24:18 +01:00
JanLJL
9f715c0ba3 added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes 2023-03-03 15:11:40 +01:00
JanLJL
2884d17971 enabled indexing without shape and lane for vector regs 2023-03-03 14:41:48 +01:00
JanLJL
dbfba9ce5b added another instruction 2023-03-03 14:39:28 +01:00
JanLJL
841a4a5724 resolve #81 2023-03-02 15:50:13 +01:00
Décio Luiz Gazzoni Filho
19c47db3ed Support for flags and conditional ops on AArch64 2023-02-19 22:08:42 -03:00
JanLJL
06bc51ba63 version bump v0.4.13 2023-02-15 19:03:11 +01:00
JanLJL
27f408e4a3 new black formatting 2023-02-15 18:54:53 +01:00
JanLJL
13c75a3312 new black formatting 2023-02-15 18:46:20 +01:00
JanLJL
98f28a7c01 exclude .ipynb files 2023-02-15 17:00:05 +01:00
JanLJL
c3001e6ecb exclude .ipynb files 2023-02-15 16:59:19 +01:00
JanLJL
b20f5539bf black formatting 2023-02-15 16:53:26 +01:00