JanLJL bc91ab3b70 Merge branch 'master' of github.com:RRZE-HPC/OSACA

2026-01-23 12:42:27 +01:00

..

test_files

take +- operator of offset/index in mem-addr into account

2025-03-14 18:46:12 +01:00

__init__.py

made tests a module

2019-10-25 14:49:21 +02:00

all_tests.py

Validation (#71)

2021-04-15 14:42:37 +02:00

test_base_parser.py

renamed .asm files to .s for consistency

2025-03-05 09:36:07 +01:00

test_cli.py

add test case for specific syntax parameter in get_asm_parser()

2025-03-04 17:45:19 +01:00

test_db_interface.py

moved get_full_instruction_name() from HardwareModel to DBInterface

2024-05-02 16:25:41 +02:00

test_frontend.py

bugfixes

2025-03-04 17:46:37 +01:00

test_marker_utils.py

renamed .asm files to .s for consistency

2025-03-05 09:36:07 +01:00

test_parser_AArch64.py

fixed imprecise operand comparison

2026-01-14 11:08:53 +01:00

test_parser_x86att.py

fixed imprecise operand comparison

2026-01-14 11:08:53 +01:00

test_parser_x86intel.py

Add tests for negative offset directly after identifier and after a space as well

2026-01-20 09:58:54 +01:00

test_semantics.py

fixed bug in DFS for instruction forms with multiple port_pressure assignments + test

2026-01-22 17:56:16 +01:00