JanLJL
|
45847e69ff
|
formatting for black
|
2025-08-16 14:13:29 +02:00 |
|
JanLJL
|
94cb3de6a1
|
fix bug to support 0x.. and ..R hex values for intel syntax
|
2025-08-16 14:08:43 +02:00 |
|
pleroy
|
df0351d087
|
Readying.
|
2025-03-31 20:48:39 +02:00 |
|
pleroy
|
969500d79f
|
Merge test
|
2025-03-31 20:47:46 +02:00 |
|
pleroy
|
af9c10f308
|
Cleanup.
|
2025-03-31 20:45:01 +02:00 |
|
pleroy
|
4255c11010
|
The tests are passing.
|
2025-03-31 20:44:36 +02:00 |
|
pleroy
|
1eb82a6f0a
|
Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.
|
2025-03-27 22:47:32 +01:00 |
|
JanLJL
|
7930e4d704
|
take +- operator of offset/index in mem-addr into account
|
2025-03-14 18:46:12 +01:00 |
|
pleroy
|
d61330404b
|
Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle.
I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.
|
2025-03-12 22:26:38 +01:00 |
|
JanLJL
|
2cf2bf5cec
|
Merge branch 'master' into merge-branch
|
2025-03-07 14:45:44 +01:00 |
|
JanLJL
|
4e3994fec1
|
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
|
2025-03-07 11:49:14 +01:00 |
|
JanLJL
|
796256fa13
|
more black formatting
|
2025-03-05 10:40:18 +01:00 |
|
JanLJL
|
02716e7b41
|
flake8 formatting
|
2025-03-05 10:19:10 +01:00 |
|
JanLJL
|
5cd6b2cf9d
|
renamed .asm files to .s for consistency
|
2025-03-05 09:36:07 +01:00 |
|
JanLJL
|
be3622ce86
|
bugfixes
|
2025-03-04 17:46:37 +01:00 |
|
JanLJL
|
63774e65bc
|
chmod +x
|
2025-03-04 17:46:23 +01:00 |
|
JanLJL
|
796cfdc3b5
|
add test case for specific syntax parameter in get_asm_parser()
|
2025-03-04 17:45:19 +01:00 |
|
pleroy
|
1a7c1588f6
|
Add support for the Intel syntax supported by MSVC and ICC
|
2025-02-02 14:02:16 +01:00 |
|
JanLJL
|
6ea61d8893
|
formatting
|
2024-08-19 15:52:28 +02:00 |
|
Markus Büttner
|
0e69fa1e26
|
Update parsing of memory segments
This addresses issue discussed in RRZE-HPC/OSACA#107.
Now it can parse instructions of the form
%fs:var@RELOC
%fs:var@RELOC+4
%fs:var@RELOC(%rdi)
|
2024-07-30 16:02:16 +02:00 |
|
JanLJL
|
d623115b1b
|
formattign
|
2024-05-02 16:30:11 +02:00 |
|
JanLJL
|
5da00d0ae6
|
moved get_full_instruction_name() from HardwareModel to DBInterface
|
2024-05-02 16:25:41 +02:00 |
|
stefandesouza
|
78309574ac
|
added prefetch operand
|
2024-03-18 22:29:39 +01:00 |
|
stefandesouza
|
4fd59eb0d0
|
Black formatting
|
2024-03-05 12:14:05 +01:00 |
|
stefandesouza
|
d884f74f5e
|
Uncommented tests
|
2024-03-05 00:19:29 +01:00 |
|
stefandesouza
|
5f9de2c41d
|
Dump now converts classes to dicts
|
2024-03-05 00:18:45 +01:00 |
|
stefandesouza
|
38781ecc94
|
Port pressure returned in tuple with Memory Operand
|
2024-03-04 20:00:43 +01:00 |
|
stefandesouza
|
1c0708e750
|
Added updated files
|
2024-02-27 14:47:55 +01:00 |
|
stefandesouza
|
d858827a47
|
Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples
|
2024-02-24 21:03:15 +01:00 |
|
stefandesouza
|
7ad3438af5
|
Removed comments from operands
|
2024-02-24 14:15:25 +01:00 |
|
stefandesouza
|
ec798f61b2
|
More formatting
|
2024-01-10 13:26:50 +01:00 |
|
stefandesouza
|
1fb015b312
|
Formatting before PR
|
2024-01-10 13:05:27 +01:00 |
|
stefandesouza
|
226bc8eee0
|
Added shift and shift_op to Register Operand
|
2024-01-04 14:34:36 +01:00 |
|
stefandesouza
|
cb5e0bdc38
|
Merged master
|
2023-12-16 12:15:12 +01:00 |
|
stefandesouza
|
339b06bd7f
|
Linters update
|
2023-12-10 18:25:00 +01:00 |
|
stefandesouza
|
8a6ae8c701
|
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
|
2023-12-10 17:26:43 +01:00 |
|
stefandesouza
|
cac4a0ebf2
|
flake8 standards
|
2023-12-03 21:04:58 +01:00 |
|
stefandesouza
|
cef7f8098d
|
Black formatting
|
2023-12-03 17:22:11 +01:00 |
|
stefandesouza
|
93ae586745
|
Fixed semantic and marker tests. Now only dump needs to be adjusted
|
2023-12-03 16:49:33 +01:00 |
|
stefandesouza
|
2c32ccf37a
|
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
|
2023-12-02 16:56:43 +01:00 |
|
stefandesouza
|
26d65750a6
|
Fixed issue with throughput assignment
|
2023-10-30 19:32:05 +01:00 |
|
stefandesouza
|
ebb973493b
|
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
|
2023-10-29 16:36:00 +01:00 |
|
stefandesouza
|
14a2aa0b52
|
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
|
2023-10-29 13:52:49 +01:00 |
|
stefandesouza
|
e0a2ea9eb2
|
Hidden operands and dependency break in iforms now included
|
2023-10-23 21:54:58 +02:00 |
|
stefandesouza
|
c171a11101
|
Updated db_interface files to work with class objects
|
2023-10-23 18:19:35 +02:00 |
|
stefandesouza
|
33d1eec106
|
Updated tests to use the now class style iforms in isa_data
|
2023-10-23 16:25:31 +02:00 |
|
stefandesouza
|
db02359ea2
|
frontend tests now use new OO style, removed AttrDict usage
|
2023-10-22 16:43:46 +02:00 |
|
stefandesouza
|
6384ea2e18
|
Convert isa_data iforms to InstructionForm type
|
2023-10-17 12:28:49 +02:00 |
|
stefandesouza
|
e95278d2a2
|
Included 'source' and 'destination' attributes when loading isa data
|
2023-10-16 15:48:47 +02:00 |
|
stefandesouza
|
0b2753a78d
|
Throughput assignment adjustments
|
2023-09-25 23:20:10 +02:00 |
|