stefandesouza
db899a2709
Changing operand matching for class operand style
2023-09-25 21:35:17 +02:00
stefandesouza
42f96753c1
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
a8e5a6ad46
Converting operand types read in from YAML files
2023-09-12 00:23:59 +02:00
stefandesouza
7f4f87d192
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
615ef82f04
Changes to accomodate the new OO style
2023-08-28 15:19:46 +02:00
stefandesouza
36549dd679
Updated list/range register resolver & applied black formatting
2023-08-26 14:51:04 +02:00
stefandesouza
76f3baf74e
Removed all AttrDict() usage in parser. process_operand() now turns single registers into operands
2023-08-21 18:53:56 +02:00
stefandesouza
b06e6424f7
Added eq methods, changed AArch parser tests for class usage
2023-08-21 15:36:40 +02:00
stefandesouza
0a32c77751
Added 2 operand types and made changes for attribute usage
2023-08-20 21:01:44 +02:00
stefandesouza
ecdfc15ac5
InstrucForm class usage in AArch parser
2023-08-20 13:35:11 +02:00
stefandesouza
317816b9d3
Separate operand files with inheritance, str and repr classes
2023-08-20 12:10:07 +02:00
stefandesouza
4c74bb0d46
Merge remote-tracking branch 'origin/master' into InstrucForm
...
merge
2023-08-20 11:39:20 +02:00
stefandesouza
537076fa25
Added seperate operand class files
2023-08-20 11:38:56 +02:00
JanLJL
f856c578bf
added tests for dict output of analysis
2023-08-15 14:01:15 +02:00
stefan.desouza@outlook.com
1eb692c86f
Classes for OperandForm and Operand types
2023-08-07 15:01:48 +02:00
stefan.desouza@outlook.com
9a0474bcc1
Added DirectiveClass with comment iterator
2023-08-06 17:42:42 +02:00
stefan.desouza@outlook.com
71e2931bb0
Added InstructionForm class
2023-08-06 17:13:42 +02:00
JanLJL
54644ffb09
black-compliant formatting
2023-03-14 18:22:27 +01:00
JanLJL
0b93766bdd
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
d1201ace11
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
7e6eb7ce58
bugfix, resolved #90
2023-03-07 17:05:31 +01:00
JanLJL
9f715c0ba3
added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes
2023-03-03 15:11:40 +01:00
JanLJL
2884d17971
enabled indexing without shape and lane for vector regs
2023-03-03 14:41:48 +01:00
JanLJL
27f408e4a3
new black formatting
2023-02-15 18:54:53 +01:00
JanLJL
13c75a3312
new black formatting
2023-02-15 18:46:20 +01:00
JanLJL
b20f5539bf
black formatting
2023-02-15 16:53:26 +01:00
JanLJL
7724ce27c7
added Zen3 support
2022-09-27 18:39:14 +02:00
JanLJL
f96f5d7ad1
black formatting
2022-06-22 17:12:53 +02:00
JanLJL
d81c53ef91
fixed #88
2022-06-22 17:09:24 +02:00
JanLJL
d418c16f4a
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
090c24ade1
fixed parsing of reg ranges and lists
2021-06-01 00:10:05 +02:00
JanLJL
d59b100fa8
changed immediate type from str to int
2021-05-10 01:12:30 +02:00
JanLJL
2f4849f44e
added tests for timeout in LCD analyis
2021-05-02 22:48:22 +02:00
Julian Hammer
9ec7c161ab
added missing testfile for sve instructions
2021-05-02 21:44:17 +02:00
Julian Hammer
88d5094bf1
Merge branch 'master' of github.com:RRZE-HPC/OSACA
2021-04-23 13:18:23 +02:00
Julian Hammer
1f32252f91
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
08440ed5e1
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
b7625a4a25
making flake8 happy
2021-03-11 12:29:14 +01:00
Julian Hammer
7da2f5bd7b
fixed output redirection
2021-03-11 12:17:46 +01:00
Julian Hammer
6204c90934
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
1ebe5ecfbd
sanity check validity of operand entries
2021-03-11 11:38:25 +01:00
JanLJL
f8d53a69d7
changed test after adjustment in parser
2021-02-25 08:12:10 +01:00
JanLJL
81ce395115
added the possibility of a 5th operand
2020-12-06 18:05:59 +01:00
JanLJL
c204096d74
fixed typo
2020-11-11 14:11:00 +01:00
JanLJL
dea217c12c
fixed test after changing TP value of instruction
2020-11-11 14:04:07 +01:00
Julian Hammer
314ff4cf9d
improved performance of arch_semantics and reg dependency matching
2020-11-09 19:27:47 +01:00
JanLJL
c8c077a834
enhanced length warning
2020-11-06 15:49:13 +01:00
JanLJL
26ee005adc
added missing test file
2020-11-06 15:07:57 +01:00
JanLJL
207c53aaad
minor bugfix in HW model and added user warnings for more insight
2020-11-06 15:06:36 +01:00
JanLJL
b986d7eba0
added --lines option
2020-11-06 12:57:41 +01:00
