Metehan Dundar 1c2be468d9 Merge branch 'master' into dev/risc-v

2025-05-08 12:23:22 +02:00

..

test_files

Merge branch 'master' into dev/risc-v

2025-05-08 12:23:22 +02:00

__init__.py

made tests a module

2019-10-25 14:49:21 +02:00

all_tests.py

Add RISCV parser to test suite

2025-03-11 11:42:15 +01:00

test_base_parser.py

renamed .asm files to .s for consistency

2025-03-05 09:36:07 +01:00

test_cli.py

add test case for specific syntax parameter in get_asm_parser()

2025-03-04 17:45:19 +01:00

test_db_interface.py

moved get_full_instruction_name() from HardwareModel to DBInterface

2024-05-02 16:25:41 +02:00

test_frontend.py

bugfixes

2025-03-04 17:46:37 +01:00

test_marker_utils.py

renamed .asm files to .s for consistency

2025-03-05 09:36:07 +01:00

test_parser_AArch64.py

added support for <Xd>! registers and [<Xd>]! mem addresses in Arm

2025-03-07 11:49:14 +01:00

test_parser_RISCV.py

Add RISC-V support and update version to 0.6.2

2025-03-21 17:16:39 +01:00

test_parser_x86att.py

formatting

2024-08-19 15:52:28 +02:00

test_parser_x86intel.py

take +- operator of offset/index in mem-addr into account

2025-03-14 18:46:12 +01:00

test_semantics.py

Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.

2025-03-27 22:47:32 +01:00