Logo
Explore Help
Register Sign In
Lerking/OSACA
1
0
Fork 0
You've already forked OSACA
mirror of https://github.com/RRZE-HPC/OSACA.git synced 2025-12-16 09:00:05 +01:00
Code Issues Packages Projects Releases Wiki Activity
Files
3456f6e24a5a89ecb73ed00a090415660c6c5da1
OSACA/osaca
History
pleroy 3456f6e24a After egg’s review.
2025-03-31 20:48:52 +02:00
..
data
Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.
2025-03-27 22:47:32 +01:00
parser
take +- operator of offset/index in mem-addr into account
2025-03-14 18:46:12 +01:00
semantics
After egg’s review.
2025-03-31 20:48:52 +02:00
__init__.py
version bump
2025-03-17 10:28:06 +01:00
__main__.py
added __main__.py
2020-11-09 08:27:31 +01:00
db_interface.py
moved get_full_instruction_name() from HardwareModel to DBInterface
2024-05-02 16:25:41 +02:00
frontend.py
Black formatting
2024-05-02 17:04:56 +02:00
osaca.py
Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/
2025-03-12 00:35:01 +01:00
utils.py
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
Powered by Gitea Version: 1.25.2 Page: 526ms Template: 17ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API