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mirror of https://github.com/RRZE-HPC/OSACA.git synced 2025-12-15 16:40:05 +01:00
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OSACA/osaca
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pleroy 88d3f1a7a0 Fix a Flake8 diagnostic.
2025-07-29 18:55:51 +02:00
..
data
Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.
2025-03-27 22:47:32 +01:00
parser
take +- operator of offset/index in mem-addr into account
2025-03-14 18:46:12 +01:00
semantics
Fix a Flake8 diagnostic.
2025-07-29 18:55:51 +02:00
__init__.py
version bump
2025-03-17 10:28:06 +01:00
__main__.py
added __main__.py
2020-11-09 08:27:31 +01:00
db_interface.py
moved get_full_instruction_name() from HardwareModel to DBInterface
2024-05-02 16:25:41 +02:00
frontend.py
Skip non-integer line numbers in frontend
2025-03-31 22:44:57 +02:00
osaca.py
Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/
2025-03-12 00:35:01 +01:00
utils.py
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
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