50 Commits

Author	SHA1	Message	Date
Andreas Abel	daf178a42b	minor fix	2021-12-10 00:21:07 +01:00
Andreas Abel	03f9ae5b26	extended cpuid	2021-12-09 16:13:14 +01:00
Andreas Abel	d6ceaf5db4	implicit index	2021-11-23 16:09:34 +01:00
Andreas Abel	b1884b72bf	update	2021-11-17 16:43:06 +01:00
Andreas Abel	04bfd842a4	make fixed counters optional	2021-10-29 17:32:59 +02:00
Andreas Abel	fc038541df	support for Rocket Lake	2021-05-28 16:59:43 +02:00
Andreas Abel	77e4985307	Issue #23	2021-04-26 16:09:11 +02:00
Andreas Abel	2198ebbb65	minor fix	2021-04-01 20:35:19 +02:00
Andreas Abel	0d35f82778	fix for AMD doc	2021-03-26 01:13:10 +01:00
Andreas Abel	e7c90594e5	improved div_cycles	2021-03-24 20:14:42 +01:00
Andreas Abel	313aa5ee30	python 3	2021-03-13 21:04:52 +01:00
Andreas Abel	ca7f63370b	changed replPolicy.py default sets	2021-03-12 16:34:14 +01:00
Andreas Abel	d44696f06e	additional LEA variants	2021-03-12 16:14:32 +01:00
Andreas Abel	5df54f1d1d	support for Tiger Lake	2021-03-09 22:31:05 +01:00
Andreas Abel	4971d6c23a	added -df option	2021-03-03 15:47:23 +01:00
Andreas Abel	1d4f3a458a	immzero variants	2021-01-23 16:13:20 +01:00
Andreas Abel	d0f2ba9cc9	padding	2021-01-13 16:07:56 +01:00
Andreas Abel	9ce44e1079	high8 registers	2021-01-04 20:51:23 +01:00
Andreas Abel	a3e586dc12	new extensions	2020-12-04 20:08:22 +01:00
Andreas Abel	1765470b65	complex decoders	2020-11-17 16:12:18 +01:00
Andreas Abel	b86665c1c2	complex decoder	2020-11-16 23:30:27 +01:00
Bartosz Taudul	91cb312015	Add missing checks for AVX512VL. ... There is one variant of VPCLMULQDQ which requires AVX512F instead. Couldn't be bothered to find which one it is.	2020-11-15 17:26:53 +01:00
Bartosz Taudul	210e09b7ab	Add ZEN3 to cpuBench.py.	2020-11-12 23:41:35 +01:00
Bartosz Taudul	d87adcc19e	Add workaround for Zen 3 L3 cache associativity.	2020-11-12 23:37:01 +01:00
Bartosz Taudul	428b37cd51	Add ZEN3 uarch to CPUID tool.	2020-11-12 23:24:26 +01:00
Andreas Abel	bf0906750b	support for Cascade Lake	2020-10-27 21:48:46 +01:00
Andreas Abel	c3879089b4	minor changes	2020-08-07 15:37:30 +02:00
Andreas Abel	b78a1d3b38	minor changes	2020-08-05 20:18:46 +02:00
Andreas Abel	52231f9a36	macro fusion	2020-08-03 19:54:11 +02:00
Andreas Abel	8f7401178e	support for indexed addressing modes	2020-07-31 15:33:40 +02:00
Andreas Abel	275f97a49e	add URLs to XML file	2020-05-26 22:42:56 +02:00
Andreas Abel	47101197a9	partial reg latencies	2020-05-11 16:11:12 +02:00
Andreas Abel	f9d352cb54	LEA latencies	2020-05-10 21:44:47 +02:00
Andreas Abel	cc66b35dec	movzx same reg	2020-05-08 00:00:23 +02:00
Andreas Abel	be71cd8bdf	x64_lib	2020-05-06 00:15:27 +02:00
Andreas Abel	b7315a4dfb	benchmarks	2020-03-19 21:54:32 +01:00
Andreas Abel	33f91e811a	update defaults	2020-03-03 22:58:11 +01:00
Andreas Abel	fe6616e552	minor change	2020-01-17 16:08:33 +01:00
Andreas Abel	917c46a462	nClearAddresses	2020-01-16 15:24:33 +01:00
Andreas Abel	925d648b9d	minor change	2020-01-11 20:19:29 +01:00
Andreas Abel	7655c3989f	option for not using other slices for clearing HL caches	2020-01-09 01:30:09 +01:00
Andreas Abel	4e7954ff5d	support for other slices	2020-01-07 23:48:12 +01:00
Andreas Abel	d41d0b7681	improved set dueling approach	2019-12-30 22:37:19 +01:00
Andreas Abel	d70535f210	support for overriding cache sets	2019-12-30 22:34:38 +01:00
Andreas Abel	e3629ead9b	wbinvd in access sequences	2019-12-02 17:42:37 +01:00
Andreas Abel	6e63f0404b	Ice Lake support	2019-11-08 15:57:52 +01:00
Andreas Abel	2e2e720ff7	update README	2019-10-22 18:24:48 +02:00
Andreas Abel	7196654a3b	minor fix	2019-09-24 15:14:44 +02:00
Andreas Abel	a6410a54c6	update README	2019-09-24 15:02:29 +02:00
Andreas Abel	9c075f04a5	nanoBench Cache Analyzer	2019-09-24 14:48:08 +02:00