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dev/risc-v
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331 Commits

Author SHA1 Message Date
Metehan Dundar
ebf76caa18 Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames 
- Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support
- Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.)
- Renamed example files from rv6 to rv64 for consistency
- Updated related configuration and test files
- All 115 tests pass successfully
 2025-07-11 18:15:51 +02:00
Metehan Dundar
61b52dbf28 RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests 
- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
 2025-06-30 00:28:52 +02:00
Metehan Dundar
480c0dcac0 Merge branch 'master' into dev/risc-v 2025-05-08 12:23:22 +02:00
Metehan Dundar
aa3753d024 Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files 2025-05-08 11:57:06 +02:00
pleroy
939089030b Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write. 2025-03-27 22:47:32 +01:00
Robin Leroy
d2b8b7771f ucomisd is like comisd 2025-03-27 22:46:48 +01:00
pleroy
ea59056f94 Define comisd sources. 2025-03-27 22:46:38 +01:00
Metehan Dundar
d782f06e84 Add RISC-V support and update version to 0.6.2 2025-03-21 17:16:39 +01:00
Robin Leroy
122f8a674b Configure the dependencies of the jmeow instructions on flags 2025-03-20 22:30:00 +01:00
Robin Leroy
94f32c51a7 Add the setmeow instructions 2025-03-20 22:29:51 +01:00
Metehan Dundar
850f7edc6b RISCV.yml file has been updated. 2025-03-13 09:54:06 +01:00
Metehan Dundar
653c27135d Add initial support for RISC-V architecture and update relevant files 2025-03-11 05:10:03 +01:00
pleroy
b4d342266d Add support for the Intel syntax supported by MSVC and ICC 2025-02-02 14:02:16 +01:00
JanLJL
dffea6d066 bugfix 2025-01-09 17:11:21 +01:00
JanLJL
02d989fe48 more SVE instructions 2025-01-09 16:48:48 +01:00
JanLJL
7e2b2ad675 added vfmaddsub instructions 2024-12-31 13:46:44 +01:00
JanLJL
58c13cef8c added vshufp[sd] instructions 2024-12-31 13:46:30 +01:00
JanLJL
67164aa7cb added instructions 2024-11-26 16:57:39 +01:00
JanLJL
0eb656071a instruction updates 2024-10-11 16:28:49 +02:00
JanLJL
dcfc7ac0db DB updates 2024-10-11 15:57:36 +02:00
JanLJL
2d54ae6ea7 added scatter instructions 2024-10-10 18:20:38 +02:00
JanLJL
1ce8cbc70f instructions updated 2024-09-08 09:35:14 +02:00
JanLJL
655e7b1faa updated instructions 2024-09-05 15:54:11 +02:00
JanLJL
e3b5c5195d more instructions 2024-09-05 10:41:16 +02:00
JanLJL
4f04bcd497 bugfix 2024-09-05 08:42:11 +02:00
JanLJL
c97cfa7309 bugfix 2024-09-04 10:59:27 +02:00
JanLJL
0a160a95b3 introduced data ports for more accurate load/store 2024-09-03 14:23:37 +02:00
JanLJL
8be2803a9f fixed pre-/post-indexed keyword 2024-09-03 14:23:14 +02:00
JanLJL
8f84368db9 initial support ZEN 4 2024-08-30 17:41:45 +02:00
JanLJL
3c335bd83d updated DB 2024-08-19 15:31:55 +02:00
JanLJL
aeee58e98e formatting 2024-05-03 12:36:30 +02:00
JanLJL
948849981b added missing TP entries and removed duplicates 2024-05-03 12:31:50 +02:00
JanLJL
76a3939479 formatting 2024-05-03 12:31:25 +02:00
JanLJL
b11a1c7cf7 Merge branch 'master' into feat/spr 2024-05-02 21:19:10 +02:00
JanLJL
88bc756d6c DB update 2024-05-02 21:17:57 +02:00
JanLJL
46a67211bc initial support for SPR 2024-03-06 00:52:06 +01:00
stefandesouza
e253638cb7 Black formatting 2024-03-05 12:14:05 +01:00
stefandesouza
cde4fb8ecf Merge remote-tracking branch 'origin/master' into InstrucForm 2024-03-05 12:12:43 +01:00
JanLJL
76c1692f5b initial support Neoverse V2 2024-03-04 20:45:48 +01:00
stefandesouza
686c769397 Reverted comment 2024-02-22 13:47:47 +01:00
stefandesouza
2c3334680e Merge branch 'InstrucForm' of https://github.com/RRZE-HPC/OSACA into InstrucForm 2024-02-22 13:45:04 +01:00
stefandesouza
40c6b71d5e Restore deleted files 2024-02-22 13:37:13 +01:00
JanLJL
6f4ebf2c6b changed post/pre-indexed key in M1 file 2024-02-08 10:17:18 +01:00
Jan
a64ececdb1 Added bge instruction 2024-02-01 10:42:35 +01:00
Jan
8a7f3f2518 Support more branching commands 2024-02-01 10:39:40 +01:00
stefandesouza
b8e88f9319 Merge remote-tracking branch 'origin/master' into InstrucForm 2023-12-16 12:14:36 +01:00
JanLJL
b2f49bdf6a added M1 arch 2023-12-12 18:33:24 +01:00
JanLJL
b7ff0b1461 bugfixes for SP reg and ccodes 2023-12-12 18:32:43 +01:00
JanLJL
54ae98d337 Merge branch 'master' into feat/m1 2023-12-12 15:58:24 +01:00
stefandesouza
37ca6670c7 pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also 2023-12-02 16:56:43 +01:00