9 Commits

Author	SHA1	Message	Date
JanLJL	187473b72c	fixed bugs in x86intel parser (ZMM and masking support)	2025-09-08 16:35:36 +02:00
JanLJL	45847e69ff	formatting for black	2025-08-16 14:13:29 +02:00
JanLJL	94cb3de6a1	fix bug to support 0x.. and ..R hex values for intel syntax	2025-08-16 14:08:43 +02:00
JanLJL	7930e4d704	take +- operator of offset/index in mem-addr into account	2025-03-14 18:46:12 +01:00
pleroy	d61330404b	Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. ... I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.	2025-03-12 22:26:38 +01:00
JanLJL	9c2f559983	black formatting	2025-03-05 10:20:47 +01:00
JanLJL	02716e7b41	flake8 formatting	2025-03-05 10:19:10 +01:00
JanLJL	400be352e1	remove dependency on MachineModel	2025-03-04 17:42:52 +01:00
pleroy	1a7c1588f6	Add support for the Intel syntax supported by MSVC and ICC	2025-02-02 14:02:16 +01:00