224 Commits

Author	SHA1	Message	Date
stefandesouza	cef7f8098d	Black formatting	2023-12-03 17:22:11 +01:00
stefandesouza	93ae586745	Fixed semantic and marker tests. Now only dump needs to be adjusted	2023-12-03 16:49:33 +01:00
stefandesouza	2c32ccf37a	pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also	2023-12-02 16:56:43 +01:00
stefandesouza	26d65750a6	Fixed issue with throughput assignment	2023-10-30 19:32:05 +01:00
stefandesouza	ebb973493b	Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working	2023-10-29 16:36:00 +01:00
stefandesouza	14a2aa0b52	Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class	2023-10-29 13:52:49 +01:00
stefandesouza	e0a2ea9eb2	Hidden operands and dependency break in iforms now included	2023-10-23 21:54:58 +02:00
stefandesouza	c171a11101	Updated db_interface files to work with class objects	2023-10-23 18:19:35 +02:00
stefandesouza	33d1eec106	Updated tests to use the now class style iforms in isa_data	2023-10-23 16:25:31 +02:00
stefandesouza	db02359ea2	frontend tests now use new OO style, removed AttrDict usage	2023-10-22 16:43:46 +02:00
stefandesouza	6384ea2e18	Convert isa_data iforms to InstructionForm type	2023-10-17 12:28:49 +02:00
stefandesouza	e95278d2a2	Included 'source' and 'destination' attributes when loading isa data	2023-10-16 15:48:47 +02:00
stefandesouza	0b2753a78d	Throughput assignment adjustments	2023-09-25 23:20:10 +02:00
stefandesouza	db899a2709	Changing operand matching for class operand style	2023-09-25 21:35:17 +02:00
stefandesouza	42f96753c1	Black formatting	2023-09-12 12:45:28 +02:00
stefandesouza	a8e5a6ad46	Converting operand types read in from YAML files	2023-09-12 00:23:59 +02:00
stefandesouza	7f4f87d192	Changes for operand matching, instruction loading	2023-09-11 18:23:57 +02:00
stefandesouza	615ef82f04	Changes to accomodate the new OO style	2023-08-28 15:19:46 +02:00
stefandesouza	b06e6424f7	Added eq methods, changed AArch parser tests for class usage	2023-08-21 15:36:40 +02:00
stefandesouza	0a32c77751	Added 2 operand types and made changes for attribute usage	2023-08-20 21:01:44 +02:00
stefan.desouza@outlook.com	1eb692c86f	Classes for OperandForm and Operand types	2023-08-07 15:01:48 +02:00
JanLJL	1125e4c5d9	fixed UnboundLocalError if tp assignment loop is not executed	2023-07-17 14:52:22 +02:00
JanLJL	c6ed492db3	fixed read out of store TP from DB	2023-06-20 21:20:41 +02:00
JanLJL	0b93766bdd	Merge branch 'master' into pr-armcc	2023-03-14 17:50:48 +01:00
JanLJL	d1201ace11	added more dependency analysis for post/pre indexing and condition flags	2023-03-14 17:00:02 +01:00
JanLJL	7e6eb7ce58	bugfix, resolved #90	2023-03-07 17:05:31 +01:00
JanLJL	f06f767c34	formatting according to black	2023-03-03 15:24:18 +01:00
JanLJL	9f715c0ba3	added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes	2023-03-03 15:11:40 +01:00
Décio Luiz Gazzoni Filho	19c47db3ed	Support for flags and conditional ops on AArch64	2023-02-19 22:08:42 -03:00
JanLJL	7c907e2432	bugfix in store throughput calculation	2022-09-28 14:21:46 +02:00
JanLJL	7724ce27c7	added Zen3 support	2022-09-27 18:39:14 +02:00
JanLJL	ddff8c5012	added option of explicitly mentioning k regs in DB (not simply gpr)	2022-09-07 10:33:16 +02:00
JanLJL	671f7f5591	added ICX architecture	2022-08-29 11:14:56 +02:00
JanLJL	d81c53ef91	fixed #88	2022-06-22 17:09:24 +02:00
JanLJL	93c0753db3	formatting	2022-04-07 12:17:08 +02:00
JanLJL	9c966c2359	small bugfixes	2022-03-17 16:38:28 +01:00
JanLJL	e1a5272fdf	formatting	2022-01-27 10:12:00 +01:00
JanLJL	d2a4749c39	added lane comparison for AArch64 reg operands	2022-01-26 14:24:48 +01:00
Qingcai Jiang	e70229aa32	Merge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 21:33:42 +08:00
Qingcai Jiang	71b9a17ab8	fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64	2021-12-30 21:32:29 +08:00
Qingcai Jiang	203ea2dfb0	XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 20:32:34 +08:00
Qingcai Jiang	0e984f4ec7	fix a bug when 'mov' is the last instruction	2021-12-30 20:30:43 +08:00
Qingcai Jiang	7194e79beb	simple implement for TSV110	2021-11-06 16:04:16 +08:00
JanLJL	df26edd075	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2021-11-04 12:09:57 +01:00
JanLJL	ba45038ad7	add latency of last instruction in CP	2021-11-04 11:58:40 +01:00
JanLJL	9c16f8bc56	formatted	2021-10-14 10:59:55 +02:00
JanLJL	5735291d27	Merge branch 'master' into a72	2021-10-14 10:37:05 +02:00
JanLJL	5205cb5cc6	fixed formatting with correct line length	2021-10-04 15:00:17 +02:00
JanLJL	e6ce870ca0	black formatting	2021-10-04 14:33:28 +02:00
JanLJL	566fbc6bc4	black conformity	2021-09-30 15:53:56 +02:00