pleroy
df0351d087
Readying.
2025-03-31 20:48:39 +02:00
pleroy
969500d79f
Merge test
2025-03-31 20:47:46 +02:00
pleroy
af9c10f308
Cleanup.
2025-03-31 20:45:01 +02:00
pleroy
4255c11010
The tests are passing.
2025-03-31 20:44:36 +02:00
pleroy
1eb82a6f0a
Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.
2025-03-27 22:47:32 +01:00
JanLJL
2cf2bf5cec
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
4e3994fec1
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
796256fa13
more black formatting
2025-03-05 10:40:18 +01:00
JanLJL
02716e7b41
flake8 formatting
2025-03-05 10:19:10 +01:00
JanLJL
5cd6b2cf9d
renamed .asm files to .s for consistency
2025-03-05 09:36:07 +01:00
pleroy
1a7c1588f6
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
5da00d0ae6
moved get_full_instruction_name() from HardwareModel to DBInterface
2024-05-02 16:25:41 +02:00
stefandesouza
4fd59eb0d0
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
d858827a47
Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples
2024-02-24 21:03:15 +01:00
stefandesouza
ec798f61b2
More formatting
2024-01-10 13:26:50 +01:00
stefandesouza
cac4a0ebf2
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
cef7f8098d
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
93ae586745
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
2c32ccf37a
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
26d65750a6
Fixed issue with throughput assignment
2023-10-30 19:32:05 +01:00
stefandesouza
ebb973493b
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
14a2aa0b52
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
e0a2ea9eb2
Hidden operands and dependency break in iforms now included
2023-10-23 21:54:58 +02:00
stefandesouza
33d1eec106
Updated tests to use the now class style iforms in isa_data
2023-10-23 16:25:31 +02:00
stefandesouza
6384ea2e18
Convert isa_data iforms to InstructionForm type
2023-10-17 12:28:49 +02:00
stefandesouza
e95278d2a2
Included 'source' and 'destination' attributes when loading isa data
2023-10-16 15:48:47 +02:00
stefandesouza
0b2753a78d
Throughput assignment adjustments
2023-09-25 23:20:10 +02:00
stefandesouza
db899a2709
Changing operand matching for class operand style
2023-09-25 21:35:17 +02:00
stefandesouza
42f96753c1
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
a8e5a6ad46
Converting operand types read in from YAML files
2023-09-12 00:23:59 +02:00
stefandesouza
7f4f87d192
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
615ef82f04
Changes to accomodate the new OO style
2023-08-28 15:19:46 +02:00
JanLJL
54644ffb09
black-compliant formatting
2023-03-14 18:22:27 +01:00
JanLJL
0b93766bdd
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
d1201ace11
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
7e6eb7ce58
bugfix, resolved #90
2023-03-07 17:05:31 +01:00
JanLJL
9f715c0ba3
added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes
2023-03-03 15:11:40 +01:00
JanLJL
7724ce27c7
added Zen3 support
2022-09-27 18:39:14 +02:00
JanLJL
d418c16f4a
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
2f4849f44e
added tests for timeout in LCD analyis
2021-05-02 22:48:22 +02:00
Julian Hammer
1f32252f91
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
08440ed5e1
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
b7625a4a25
making flake8 happy
2021-03-11 12:29:14 +01:00
Julian Hammer
6204c90934
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
314ff4cf9d
improved performance of arch_semantics and reg dependency matching
2020-11-09 19:27:47 +01:00
Julian Hammer
9d2ea8603f
new caching structure with support for distribution
2020-10-28 16:29:55 +01:00
JanLJL
cd5a706f56
adjusted tests for AArch64
2020-10-15 17:56:08 +02:00
JanLJL
c9000f74bc
enabled kerncraft marker insertion for aarch64 and more tests
2020-02-27 16:00:23 +01:00
JanLJL
2d30d190f4
running examples for tests
2020-02-26 18:40:08 +01:00
JanLJL
8cce680bd7
more tests
2020-02-26 17:32:13 +01:00
