17 Commits

Author	SHA1	Message	Date
pleroy	1a7c1588f6	Add support for the Intel syntax supported by MSVC and ICC	2025-02-02 14:02:16 +01:00
JanLJL	2bdc765df2	fixed bug in read-out of default store TP	2024-08-19 14:37:20 +02:00
stefandesouza	d858827a47	Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples	2024-02-24 21:03:15 +01:00
stefandesouza	dcfe36b850	Took out name attribute from operand parent class	2024-02-24 15:46:04 +01:00
stefandesouza	66e51630af	Memory attributes name change	2024-02-22 13:51:48 +01:00
stefandesouza	0b3508abf8	Small cleaup commit	2023-12-16 16:00:37 +01:00
stefandesouza	93ae586745	Fixed semantic and marker tests. Now only dump needs to be adjusted	2023-12-03 16:49:33 +01:00
stefandesouza	ebb973493b	Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working	2023-10-29 16:36:00 +01:00
stefandesouza	14a2aa0b52	Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class	2023-10-29 13:52:49 +01:00
stefandesouza	e95278d2a2	Included 'source' and 'destination' attributes when loading isa data	2023-10-16 15:48:47 +02:00
stefandesouza	42f96753c1	Black formatting	2023-09-12 12:45:28 +02:00
stefandesouza	a8e5a6ad46	Converting operand types read in from YAML files	2023-09-12 00:23:59 +02:00
stefandesouza	36549dd679	Updated list/range register resolver & applied black formatting	2023-08-26 14:51:04 +02:00
stefandesouza	b06e6424f7	Added eq methods, changed AArch parser tests for class usage	2023-08-21 15:36:40 +02:00
stefandesouza	ecdfc15ac5	InstrucForm class usage in AArch parser	2023-08-20 13:35:11 +02:00
stefandesouza	317816b9d3	Separate operand files with inheritance, str and repr classes	2023-08-20 12:10:07 +02:00
stefandesouza	537076fa25	Added seperate operand class files	2023-08-20 11:38:56 +02:00