267 Commits

Author	SHA1	Message	Date
JanLJL	1f010ecf7e	add missing instruction for test	2023-03-14 17:51:20 +01:00
JanLJL	97756faa04	Merge branch 'master' into pr-armcc	2023-03-14 17:50:48 +01:00
JanLJL	7c6de89f30	more instructions	2023-03-14 17:00:23 +01:00
JanLJL	1b261912e0	renamed condition code attrib, fixed incorrect src/dst, and added more conditional instructions	2023-03-14 16:57:34 +01:00
JanLJL	27828ec5b4	added instruction	2023-03-07 17:04:32 +01:00
JanLJL	1938e889d3	added another instruction	2023-03-03 14:39:28 +01:00
JanLJL	37c8598b36	resolve #81	2023-03-02 15:50:13 +01:00
Décio Luiz Gazzoni Filho	b434e30ec1	Support for flags and conditional ops on AArch64	2023-02-19 22:08:42 -03:00
JanLJL	ead1ffc5ca	black formatting	2023-02-15 16:53:26 +01:00
JanLJL	089a48d2bb	added more and refined instruction measurements	2023-02-15 14:24:16 +01:00
JanLJL	81f0291496	bugfix in store throughput	2023-01-23 18:42:41 +01:00
JanLJL	8a9aa298dd	updated DB	2022-12-11 17:13:56 +01:00
JanLJL	03a3894f91	more instructions	2022-10-11 15:43:19 +02:00
JanLJL	50ebca3fab	added few instrucitons	2022-10-07 00:51:09 +02:00
JanLJL	405f390e03	bugfix in store throughput calculation	2022-09-28 14:21:46 +02:00
JanLJL	ff78d03e3e	formatting for flake8	2022-09-28 10:05:18 +02:00
JanLJL	093227605f	updated and bugfixed DB	2022-09-28 10:01:26 +02:00
JanLJL	810454fc57	updated DB	2022-09-28 10:01:14 +02:00
JanLJL	d5aaceb9c4	added Zen3 support	2022-09-27 18:39:14 +02:00
JanLJL	5738d4a934	bugfixes and more features	2022-09-27 18:04:59 +02:00
JanLJL	a5bd90eff6	bugfixes	2022-09-27 18:04:33 +02:00
JanLJL	d3e5a48f47	more instruction forms	2022-09-07 12:48:39 +02:00
JanLJL	3250d87647	removed invalid char	2022-09-07 10:48:45 +02:00
JanLJL	f2338a67c6	more instruction forms	2022-09-07 10:33:28 +02:00
JanLJL	16cae13925	added more instructions for ICX	2022-09-01 15:49:28 +02:00
JanLJL	74ce449680	Merge branch 'master' of github.com:RRZE-HPC/osaca	2022-08-31 14:20:07 +02:00
JanLJL	6c4d5b5eef	added AND instr	2022-08-31 14:19:23 +02:00
JanLJL	f8a3d42314	fix bug in port util	2022-08-31 14:17:52 +02:00
JanLJL	b83c0bba8b	formatting	2022-08-29 11:30:46 +02:00
JanLJL	686fa90007	added ICX architecture	2022-08-29 11:14:56 +02:00
JanLJL	04b74327ef	version bump	2022-04-08 13:51:08 +02:00
JanLJL	dafaf600c7	a few more instructions	2022-04-08 12:02:05 +02:00
JanLJL	4b6212dc8c	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2022-04-07 10:39:16 +02:00
JanLJL	9e541dea5e	updates	2022-04-07 10:39:12 +02:00
JanLJL	7df61ba65c	removed temp file	2022-04-06 16:28:02 +02:00
Jan	b6b64edbc4	Merge pull request #84 from qcjiang/feature/tsv110 ... Feature/tsv110	2022-04-06 16:25:39 +02:00
JanLJL	6e2c58ed78	bugfixes and additions	2022-03-28 10:06:51 +02:00
Qingcai Jiang	728bb03a93	fix a bug about orr in tsv110	2022-03-20 14:53:34 +08:00
JanLJL	54da7568d9	small bugfixes	2022-03-17 16:38:28 +01:00
Qingcai Jiang	a56c972fa3	Merge branch 'feature/tsv110' of github.com:qcjiang/OSACA into feature/tsv110	2022-02-27 17:19:28 +08:00
Qingcai Jiang	d51d84afcc	adjust sshll instruction	2022-02-27 17:19:15 +08:00
Jan	86b62ecb6d	fixed typo	2022-02-14 10:42:01 +01:00
JanLJL	c9d63f7d3c	adjusted DB	2022-01-26 14:25:01 +01:00
Qingcai Jiang	0e04963ace	modify some instructions for tsv110	2022-01-06 16:25:08 +08:00
Qingcai Jiang	f8c23ce43d	add some instructions for tsv110	2022-01-04 20:59:35 +08:00
Qingcai Jiang	5d36b56e07	add some instructions for tsv110	2022-01-04 18:45:32 +08:00
Qingcai Jiang	4e5b768780	fix some instr for tsv110	2021-12-30 21:24:41 +08:00
Qingcai Jiang	e20fb21679	add some instructions for tsv110, now support most of the instructions	2021-12-19 18:13:32 +08:00
Qingcai Jiang	dc2d605d6a	add some instructions for tsv110	2021-12-18 17:51:41 +08:00
Qingcai Jiang	45b70e0961	add some instructions for tsv110	2021-12-18 15:44:07 +08:00