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Author	SHA1	Message	Date
JanLJL	2b28707185	fixed wrong import of mm registers	2020-03-17 12:56:12 +01:00
JanLJL	c59398c2df	enhanced MachineModel to support mask/zeroing differentiation for instruction forms	2020-03-17 12:55:37 +01:00
JanLJL	f1d3776d68	version bump	2020-03-16 22:02:50 +01:00
JanLJL	ac409d4a7f	added test to check all micro-archs	2020-03-16 21:31:14 +01:00
JanLJL	a2204aa333	fixed duplicates in SNB machine model	2020-03-16 17:28:08 +01:00
JanLJL	b2e1e6f930	implemented online check for src/dst of operands based on felixcloutier	2020-03-12 15:08:14 +01:00
JanLJL	08923d4141	more instruction forms and added wildcard support for registers in ISA DB	2020-03-12 15:07:51 +01:00
JanLJL	7aa8b40bd3	bugfixes	2020-03-12 15:06:02 +01:00
JanLJL	9318181902	added reg-only fallback for mem-instructions not found in ISA DB	2020-03-10 17:15:57 +01:00
JanLJL	07b51c6705	imported reg-only instructions with port util from uops.info for ZEN2	2020-03-10 14:32:31 +01:00
JanLJL	10c47f960d	with working rst file for PypPI	2020-03-10 10:10:29 +01:00
JanLJL	c84178b469	removed raw directive (now for real)	2020-03-09 17:56:18 +01:00
JanLJL	7e808f17e4	removed raw directive for PyPI	2020-03-09 17:33:39 +01:00
JanLJL	057f2fcd62	version bump	2020-03-09 16:52:07 +01:00
JanLJL	52ca93ad03	added documentation	2020-03-09 16:35:06 +01:00
JanLJL	458b5954b9	more documentation	2020-03-05 18:39:38 +01:00
JanLJL	4e435ab48f	updated docs	2020-03-05 17:13:23 +01:00
JanLJL	0bef168565	added doc badges	2020-03-05 16:56:27 +01:00
JanLJL	0d5feeda80	Merge branch 'master' of github.com:RRZE-HPC/osaca	2020-03-05 16:44:29 +01:00
JanLJL	71f5e10e8a	added Sphinx documentation for RTD	2020-03-05 16:44:18 +01:00
JanLJL	f323576fae	renamed doc to docs and more documentation	2020-03-05 15:28:30 +01:00
Julian Hammer	cf147291ff	outlined osaca logo font	2020-03-03 17:30:00 +01:00
JanLJL	7a8f5862a3	initial upload of zen2 data	2020-03-03 14:15:34 +01:00
JanLJL	e7c43fa3e7	added thesis in docs and updated logo	2020-03-03 12:52:59 +01:00
JanLJL	425a0cff65	minor fixes	2020-02-27 18:32:48 +01:00
JanLJL	d54739812a	minor fixes	2020-02-27 18:11:32 +01:00
Jan	1f75923b86	Refactoring of README and more description	2020-02-27 18:10:09 +01:00
JanLJL	dbde8c958e	reduced testing runtime	2020-02-27 16:23:56 +01:00
JanLJL	bee9857963	bugfix for kerncraft dependency	2020-02-27 16:16:07 +01:00
JanLJL	a204762fa3	enabled kerncraft marker insertion for aarch64 and more tests	2020-02-27 16:00:23 +01:00
JanLJL	2e321daa83	added missing example coverage	2020-02-27 13:56:12 +01:00
JanLJL	d439e74eea	added the ability of different output stream for running osaca and more tests	2020-02-27 13:30:58 +01:00
JanLJL	40e04f2ef0	bugfix for running graph export in test env	2020-02-26 20:02:29 +01:00
JanLJL	aa0603860b	running examples for tests	2020-02-26 18:40:08 +01:00
JanLJL	b43a962d66	more tests	2020-02-26 17:32:13 +01:00
JanLJL	32b82c7824	minor fixes and removed unnecessary load_tps	2020-02-26 15:40:52 +01:00
JanLJL	6776be5c5d	added test for optimal throughput assignment and invalid asmbench import files	2020-02-20 16:34:11 +01:00
JanLJL	17ce42dd47	bugfix	2020-02-20 12:25:50 +01:00
JanLJL	ee6ed33aac	added tests for asmbench import	2020-02-20 12:07:20 +01:00
JanLJL	8c41e2d531	more tests	2020-02-20 09:04:39 +01:00
JanLJL	3c7c0af3ba	updated codecov settings	2020-02-12 19:19:35 +01:00
Jan	3e70d1d69f	Create codecov.yml	2020-02-12 19:16:27 +01:00
Julian Hammer	05b47ff1a8	added instructions (with 2D and 3D ports) from uops.info	2020-02-05 10:07:44 +01:00
Julian Hammer	16fb39d419	adding 2D and 3D ports on combined load instructions	2020-02-05 10:07:23 +01:00
Julian Hammer	5f3572fc6c	added ice lake abbreviation	2020-02-05 10:05:57 +01:00
Jan	835caf4ba8	Added explanation for kernels	2020-02-03 13:39:12 +01:00
JanLJL	4dfd55c790	added example kernels	2020-02-03 13:19:18 +01:00
JanLJL	f2ae430c5d	small bugfix in tx2 and version update in meta data	2020-02-01 15:11:47 +01:00
JanLJL	8fb44f2606	version bump	2020-01-31 19:17:44 +01:00
Julian Hammer	465c29a12b	small change to .travis.yml	2020-01-31 17:16:42 +01:00