287 Commits

Author	SHA1	Message	Date
JanLJL	2ba04e614a	DB update	2024-05-02 21:17:57 +02:00
JanLJL	764b22cebe	initial support for SPR	2024-03-06 00:52:06 +01:00
JanLJL	3435641451	initial support Neoverse V2	2024-03-04 20:45:48 +01:00
Jan	a2b40b9d2c	Added bge instruction	2024-02-01 10:42:35 +01:00
Jan	abfce92b4b	Support more branching commands	2024-02-01 10:39:40 +01:00
JanLJL	f3b50b93f5	added M1 arch	2023-12-12 18:33:24 +01:00
JanLJL	c5ef5f7432	bugfixes for SP reg and ccodes	2023-12-12 18:32:43 +01:00
JanLJL	78387a374d	Merge branch 'master' into feat/m1	2023-12-12 15:58:24 +01:00
JanLJL	2331e4dd8f	added vbroadcast instr to ICX/ICL/SKX	2023-10-13 14:47:44 +02:00
JanLJL	dc250bcedc	initial commit of M1 model (not complete)	2023-09-28 10:04:15 +02:00
JanLJL	74478034f7	Merge branch 'master' of github.com:RRZE-HPC/osaca	2023-09-13 09:49:28 +02:00
Stephen Nicholas Swatman	7cd380e7b8	Add IMUL instruction for Zen 3 architectures ... This commit adds data on the IMUL (r, r) instruction on the AMD Zen 3 microarchitecture.	2023-08-12 19:40:44 +02:00
JanLJL	c599ce4967	fixed wrong LEA DB entry	2023-08-03 11:13:23 +02:00
JanLJL	c090d24edf	added new instructions	2023-08-02 11:04:56 +02:00
JanLJL	9f9471ee4e	changed TP/LT for reg renaming moves	2023-08-02 11:03:31 +02:00
JanLJL	1125e4c5d9	fixed UnboundLocalError if tp assignment loop is not executed	2023-07-17 14:52:22 +02:00
JanLJL	88a1efe633	fixes #93	2023-07-17 14:22:05 +02:00
JanLJL	a0d8895d38	added shift instructions	2023-07-05 16:42:34 +02:00
JanLJL	1ac20073ab	added reg specific store TP	2023-06-20 21:17:37 +02:00
JanLJL	2a43676097	added p-indexing latency values for Arm architectures	2023-03-24 17:05:45 +01:00
JanLJL	af3b1fe3e8	add missing instruction for test	2023-03-14 17:51:20 +01:00
JanLJL	0b93766bdd	Merge branch 'master' into pr-armcc	2023-03-14 17:50:48 +01:00
JanLJL	27eb8f62b6	more instructions	2023-03-14 17:00:23 +01:00
JanLJL	d6569a0f23	renamed condition code attrib, fixed incorrect src/dst, and added more conditional instructions	2023-03-14 16:57:34 +01:00
JanLJL	10d4c4b87e	added instruction	2023-03-07 17:04:32 +01:00
JanLJL	dbfba9ce5b	added another instruction	2023-03-03 14:39:28 +01:00
JanLJL	841a4a5724	resolve #81	2023-03-02 15:50:13 +01:00
Décio Luiz Gazzoni Filho	19c47db3ed	Support for flags and conditional ops on AArch64	2023-02-19 22:08:42 -03:00
JanLJL	b20f5539bf	black formatting	2023-02-15 16:53:26 +01:00
JanLJL	e6d24ea01d	added more and refined instruction measurements	2023-02-15 14:24:16 +01:00
JanLJL	bdbbfd446f	bugfix in store throughput	2023-01-23 18:42:41 +01:00
JanLJL	4c50483a83	updated DB	2022-12-11 17:13:56 +01:00
JanLJL	5c21e18e36	more instructions	2022-10-11 15:43:19 +02:00
JanLJL	8807e3eda6	added few instrucitons	2022-10-07 00:51:09 +02:00
JanLJL	7c907e2432	bugfix in store throughput calculation	2022-09-28 14:21:46 +02:00
JanLJL	2fa25e3099	formatting for flake8	2022-09-28 10:05:18 +02:00
JanLJL	0b440e4da9	updated and bugfixed DB	2022-09-28 10:01:26 +02:00
JanLJL	08e6a4be36	updated DB	2022-09-28 10:01:14 +02:00
JanLJL	7724ce27c7	added Zen3 support	2022-09-27 18:39:14 +02:00
JanLJL	4f8e37d9fd	bugfixes and more features	2022-09-27 18:04:59 +02:00
JanLJL	d5f1654aa8	bugfixes	2022-09-27 18:04:33 +02:00
JanLJL	df747b8c48	more instruction forms	2022-09-07 12:48:39 +02:00
JanLJL	4e25a29a8a	removed invalid char	2022-09-07 10:48:45 +02:00
JanLJL	016061f72c	more instruction forms	2022-09-07 10:33:28 +02:00
JanLJL	2306cb58d0	added more instructions for ICX	2022-09-01 15:49:28 +02:00
JanLJL	660a9d0f41	Merge branch 'master' of github.com:RRZE-HPC/osaca	2022-08-31 14:20:07 +02:00
JanLJL	3b453de617	added AND instr	2022-08-31 14:19:23 +02:00
JanLJL	b93d911bb7	fix bug in port util	2022-08-31 14:17:52 +02:00
JanLJL	76542782c8	formatting	2022-08-29 11:30:46 +02:00
JanLJL	671f7f5591	added ICX architecture	2022-08-29 11:14:56 +02:00