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800 Commits 2 Branches 44 Tags
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800 Commits

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Author SHA1 Message Date
Qingcai Jiang
e20fb21679 add some instructions for tsv110, now support most of the instructions 2021-12-19 18:13:32 +08:00
QCJiang
114114e553 Merge branch 'RRZE-HPC:master' into feature/tsv110 2021-12-18 17:52:54 +08:00
Qingcai Jiang
dc2d605d6a add some instructions for tsv110 2021-12-18 17:51:41 +08:00
Qingcai Jiang
45b70e0961 add some instructions for tsv110 2021-12-18 15:44:07 +08:00
Qingcai Jiang
b9c4f228b7 add some instructions for tsv110 2021-12-15 21:51:59 +08:00
Qingcai Jiang
b1f3b150fa Merge branch 'bug_fix/negative_hex_address' into feature/tsv110 2021-12-15 20:04:59 +08:00
Qingcai Jiang
871b79af90 add some instructions in tsv110.yml 2021-12-07 18:27:42 +08:00
Qingcai Jiang
3860253601 double check with every data in instructions 2021-12-07 16:58:30 +08:00
Qingcai Jiang
3b0dfc7141 formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers 2021-12-07 16:33:22 +08:00
Qingcai Jiang
a89e31350e fix latency in str/ldr instructions 2021-12-07 16:17:00 +08:00
Jan
70fd12a360 Merge pull request #82 from qcjiang/bug_fix/negative_hex_address 
fix a bug when the hex_number of address is negative
 2021-12-03 14:39:04 +01:00
Jan
b18f7bf718 black-conform formatting 2021-12-03 14:38:52 +01:00
Qingcai Jiang
3efda4ba6c fix a bug when the hex_number of address is negative 2021-12-03 15:13:54 +08:00
Qingcai Jiang
2059269d8a fix typos 2021-12-02 22:55:39 +08:00
Qingcai Jiang
be48dd6c1b add latency and TP information through ibench 2021-12-01 11:42:36 +08:00
JanLJL
fb2dbfa83f added branch instructions and data for ADD 2021-11-29 18:48:13 +01:00
JanLJL
b43f4374b1 changed data for register renaming 2021-11-29 18:39:37 +01:00
JanLJL
a111ce7e89 unfified STP and LDP instructions 2021-11-29 18:34:39 +01:00
JanLJL
fd628a0dde unified LOAD instructions 2021-11-29 17:48:16 +01:00
JanLJL
a8a6f42061 unified STORE instructions 2021-11-29 17:32:51 +01:00
JanLJL
1359cc92ba adjusted non-instruction_form fields 2021-11-29 15:17:38 +01:00
Qingcai Jiang
de0982226b add some instructions with ibench 2021-11-17 17:49:05 +08:00
Qingcai Jiang
2d38cac9a1 simple implement for TSV110 2021-11-06 16:04:16 +08:00
JanLJL
6f3b36e58c version bump 2021-11-04 14:56:23 +01:00
JanLJL
f901b481da black formatting 2021-11-04 12:11:15 +01:00
JanLJL
1d6e0d5a42 Merge branch 'master' of github.com:RRZE-HPC/OSACA 2021-11-04 12:09:57 +01:00
JanLJL
d84a6399dd Closes #78, closes #79; added unary/binary logical operators 2021-11-04 12:09:44 +01:00
JanLJL
c659aebe4b add latency of last instruction in CP 2021-11-04 11:58:40 +01:00
JanLJL
f801950ffb better output formatting 2021-11-04 11:55:48 +01:00
Jan
2995f1873d Merge pull request #60 from RRZE-HPC/a72 
Add support for ARM Cortex-A72
 2021-10-14 18:10:36 +02:00
JanLJL
c36fab40cb added Cortex A72 in README 2021-10-14 17:10:08 +02:00
JanLJL
4e967380d6 formatted 2021-10-14 10:59:55 +02:00
JanLJL
3789e065c6 formatted 2021-10-14 10:53:34 +02:00
JanLJL
3971e9e853 Merge branch 'master' into a72 2021-10-14 10:37:05 +02:00
JanLJL
3b20246fc3 unified format 2021-10-14 09:23:35 +02:00
JanLJL
8c94378437 version bump 2021-10-07 17:10:17 +02:00
JanLJL
bc7761007c fixed formatting with correct line length 2021-10-04 15:00:17 +02:00
JanLJL
314feb4104 black formatting 2021-10-04 14:33:28 +02:00
JanLJL
217fcff664 black conformity 2021-09-30 15:53:56 +02:00
JanLJL
f1f119f5a0 added instructions for BHIVE 2021-09-29 17:26:44 +02:00
JanLJL
3404d72dc5 enhanced parser 2021-09-29 17:26:27 +02:00
Jan
b2e914db4a added lint configs 2021-08-27 08:14:50 +02:00
JanLJL
1b40c10a1f applied flake8 and black rules 2021-08-26 16:58:19 +02:00
JanLJL
db30a4e36c fixed wrong uops info import with masking of some gather/scatter 2021-08-26 11:05:33 +02:00
JanLJL
44f3c0376e version bump 2021-07-21 02:41:05 +02:00
JanLJL
a721d0941d added more load instrs 2021-07-21 02:34:31 +02:00
JanLJL
2d17a48604 updated a few DB entries 2021-06-02 16:37:18 +02:00
JanLJL
98de6f2a92 version bump 2021-06-01 00:13:38 +02:00
JanLJL
ec771dbe91 fixed parsing of reg ranges and lists 2021-06-01 00:10:05 +02:00
JanLJL
8cc36e6691 version bump 2021-05-10 12:56:35 +02:00