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Author	SHA1	Message	Date
Jan	2b838b7bdd	Merge pull request #112 from pleroy/Intel ... Add support for the Intel syntax produced by MSVC and ICC	2025-03-17 10:20:40 +01:00
JanLJL	31f5912af6	take +- operator of offset/index in mem-addr into account	2025-03-14 18:46:12 +01:00
pleroy	732dd95810	Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. ... I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.	2025-03-12 22:26:38 +01:00
pleroy	f846f0ed7d	Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/	2025-03-12 00:35:01 +01:00
pleroy	e3910056cf	Revert d772522400 and fix a failure in tests.test_cli.TestCLI.test_without_arch while preserving the possibility to try more archs than the detected one.	2025-03-11 23:34:36 +01:00
JanLJL	ffb5f0eb55	Merge branch 'master' into merge-branch	2025-03-07 14:45:44 +01:00
JanLJL	bcecabd911	added support for <Xd>! registers and [<Xd>]! mem addresses in Arm	2025-03-07 11:49:14 +01:00
JanLJL	022bd2997d	add setuptools to Install	2025-03-05 13:19:09 +01:00
JanLJL	bec925d5aa	specify commit for kerncraft	2025-03-05 12:54:55 +01:00
JanLJL	461bf0306f	undo unnecessary install	2025-03-05 11:01:47 +01:00
JanLJL	585e2d6177	use local osaca version	2025-03-05 11:00:08 +01:00
JanLJL	b7e5df0a08	more black formatting	2025-03-05 10:40:18 +01:00
JanLJL	799acd5c20	install kerncraft from git repo	2025-03-05 10:38:39 +01:00
JanLJL	63f56e50b4	black formatting	2025-03-05 10:20:47 +01:00
JanLJL	fb7f1a289d	flake8 formatting	2025-03-05 10:19:10 +01:00
JanLJL	a4939d1873	renamed .asm files to .s for consistency	2025-03-05 09:36:07 +01:00
JanLJL	4e6d37aa9f	bugfixes	2025-03-04 17:46:37 +01:00
JanLJL	1c2e0f3921	chmod +x	2025-03-04 17:46:23 +01:00
JanLJL	3de6097a06	add test case for specific syntax parameter in get_asm_parser()	2025-03-04 17:45:19 +01:00
JanLJL	b6c3c924c6	remove dependency on MachineModel	2025-03-04 17:44:27 +01:00
JanLJL	1be2f320b9	add default syntax for get_parser for compatibility with kerncraft	2025-03-04 17:44:02 +01:00
JanLJL	379e422290	remove dependency on MachineModel	2025-03-04 17:42:52 +01:00
JanLJL	d772522400	fix bug when no micro arch was given	2025-03-04 17:42:05 +01:00
JanLJL	dbbbe743ac	get_marker() needed for kerncraft	2025-03-03 18:26:33 +01:00
pleroy	b4d342266d	Add support for the Intel syntax supported by MSVC and ICC	2025-02-02 14:02:16 +01:00
JanLJL	dffea6d066	bugfix	2025-01-09 17:11:21 +01:00
JanLJL	02d989fe48	more SVE instructions	2025-01-09 16:48:48 +01:00
JanLJL	7e2b2ad675	added vfmaddsub instructions	2024-12-31 13:46:44 +01:00
JanLJL	58c13cef8c	added vshufp[sd] instructions	2024-12-31 13:46:30 +01:00
JanLJL	67164aa7cb	added instructions	2024-11-26 16:57:39 +01:00
JanLJL	5e20536e63	version bump	2024-10-11 16:34:48 +02:00
JanLJL	445b47ee29	changed default ARCHs to SPR/V2	2024-10-11 16:29:13 +02:00
JanLJL	0eb656071a	instruction updates	2024-10-11 16:28:49 +02:00
JanLJL	dcfc7ac0db	DB updates	2024-10-11 15:57:36 +02:00
JanLJL	c22471eb35	Merge branch 'master' of github.com:RRZE-HPC/osaca	2024-10-10 18:35:57 +02:00
JanLJL	2d54ae6ea7	added scatter instructions	2024-10-10 18:20:38 +02:00
JanLJL	602c0a9b71	fix #109	2024-10-01 12:00:47 +02:00
JanLJL	572a1699e7	version bump	2024-09-16 21:09:12 +02:00
JanLJL	1ce8cbc70f	instructions updated	2024-09-08 09:35:14 +02:00
JanLJL	655e7b1faa	updated instructions	2024-09-05 15:54:11 +02:00
JanLJL	61485e2fdc	formatting	2024-09-05 10:44:23 +02:00
JanLJL	e3b5c5195d	more instructions	2024-09-05 10:41:16 +02:00
JanLJL	8d7e68d6aa	bugfix	2024-09-05 08:42:53 +02:00
JanLJL	4f04bcd497	bugfix	2024-09-05 08:42:11 +02:00
JanLJL	5902ef1c75	fixed formatting	2024-09-04 13:10:58 +02:00
JanLJL	69b4d1c6d4	added min version requirement for kerncraft in GHA	2024-09-04 12:53:39 +02:00
JanLJL	c97cfa7309	bugfix	2024-09-04 10:59:27 +02:00
JanLJL	f098e8628d	updated for newer uarchs	2024-09-04 09:52:32 +02:00
JanLJL	19d3a27355	added SVE reg width output in main func	2024-09-03 14:27:28 +02:00
JanLJL	0a160a95b3	introduced data ports for more accurate load/store	2024-09-03 14:23:37 +02:00