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Author	SHA1	Message	Date
JanLJL	54da7568d9	small bugfixes	2022-03-17 16:38:28 +01:00
Qingcai Jiang	a56c972fa3	Merge branch 'feature/tsv110' of github.com:qcjiang/OSACA into feature/tsv110	2022-02-27 17:19:28 +08:00
Qingcai Jiang	d51d84afcc	adjust sshll instruction	2022-02-27 17:19:15 +08:00
Qingcai Jiang	4729e24ee9	Merge branch 'pr84' into feature/tsv110	2022-02-18 16:04:55 +08:00
Qingcai Jiang	0dbd1ab48c	Merge branch 'master' into feature/tsv110	2022-02-18 16:03:25 +08:00
Jan	86b62ecb6d	fixed typo	2022-02-14 10:42:01 +01:00
Jan	633e54af90	Merge branch 'master' into feature/tsv110	2022-01-27 10:52:39 +01:00
JanLJL	babb5e1d84	formatting	2022-01-27 10:12:00 +01:00
Jan	681278ba13	Merge pull request #85 from qcjiang/bug_fix/when_mov_is_the_last_instr ... a) fix a bug when 'mov' is the last instruction and no markers are given b) fix bug when kernel consists of only unknown load instructions	2022-01-27 10:09:28 +01:00
JanLJL	c9d63f7d3c	adjusted DB	2022-01-26 14:25:01 +01:00
JanLJL	4aeb031240	added lane comparison for AArch64 reg operands	2022-01-26 14:24:48 +01:00
Qingcai Jiang	0e04963ace	modify some instructions for tsv110	2022-01-06 16:25:08 +08:00
Qingcai Jiang	f8c23ce43d	add some instructions for tsv110	2022-01-04 20:59:35 +08:00
Qingcai Jiang	5d36b56e07	add some instructions for tsv110	2022-01-04 18:45:32 +08:00
Qingcai Jiang	81fe9be3c4	Merge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 21:33:42 +08:00
Qingcai Jiang	871a8da414	fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64	2021-12-30 21:32:29 +08:00
Qingcai Jiang	4e5b768780	fix some instr for tsv110	2021-12-30 21:24:41 +08:00
Qingcai Jiang	8a899185c2	XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 20:32:34 +08:00
Qingcai Jiang	d1450517b3	fix a bug when 'mov' is the last instruction	2021-12-30 20:30:43 +08:00
Qingcai Jiang	e20fb21679	add some instructions for tsv110, now support most of the instructions	2021-12-19 18:13:32 +08:00
QCJiang	114114e553	Merge branch 'RRZE-HPC:master' into feature/tsv110	2021-12-18 17:52:54 +08:00
Qingcai Jiang	dc2d605d6a	add some instructions for tsv110	2021-12-18 17:51:41 +08:00
Qingcai Jiang	45b70e0961	add some instructions for tsv110	2021-12-18 15:44:07 +08:00
Qingcai Jiang	b9c4f228b7	add some instructions for tsv110	2021-12-15 21:51:59 +08:00
Qingcai Jiang	b1f3b150fa	Merge branch 'bug_fix/negative_hex_address' into feature/tsv110	2021-12-15 20:04:59 +08:00
Qingcai Jiang	871b79af90	add some instructions in tsv110.yml	2021-12-07 18:27:42 +08:00
Qingcai Jiang	3860253601	double check with every data in instructions	2021-12-07 16:58:30 +08:00
Qingcai Jiang	3b0dfc7141	formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers	2021-12-07 16:33:22 +08:00
Qingcai Jiang	a89e31350e	fix latency in str/ldr instructions	2021-12-07 16:17:00 +08:00
Jan	70fd12a360	Merge pull request #82 from qcjiang/bug_fix/negative_hex_address ... fix a bug when the hex_number of address is negative	2021-12-03 14:39:04 +01:00
Jan	b18f7bf718	black-conform formatting	2021-12-03 14:38:52 +01:00
Qingcai Jiang	3efda4ba6c	fix a bug when the hex_number of address is negative	2021-12-03 15:13:54 +08:00
Qingcai Jiang	2059269d8a	fix typos	2021-12-02 22:55:39 +08:00
Qingcai Jiang	be48dd6c1b	add latency and TP information through ibench	2021-12-01 11:42:36 +08:00
JanLJL	fb2dbfa83f	added branch instructions and data for ADD	2021-11-29 18:48:13 +01:00
JanLJL	b43f4374b1	changed data for register renaming	2021-11-29 18:39:37 +01:00
JanLJL	a111ce7e89	unfified STP and LDP instructions	2021-11-29 18:34:39 +01:00
JanLJL	fd628a0dde	unified LOAD instructions	2021-11-29 17:48:16 +01:00
JanLJL	a8a6f42061	unified STORE instructions	2021-11-29 17:32:51 +01:00
JanLJL	1359cc92ba	adjusted non-instruction_form fields	2021-11-29 15:17:38 +01:00
Qingcai Jiang	de0982226b	add some instructions with ibench	2021-11-17 17:49:05 +08:00
Qingcai Jiang	2d38cac9a1	simple implement for TSV110	2021-11-06 16:04:16 +08:00
JanLJL	6f3b36e58c	version bump	2021-11-04 14:56:23 +01:00
JanLJL	f901b481da	black formatting	2021-11-04 12:11:15 +01:00
JanLJL	1d6e0d5a42	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2021-11-04 12:09:57 +01:00
JanLJL	d84a6399dd	Closes #78, closes #79; added unary/binary logical operators	2021-11-04 12:09:44 +01:00
JanLJL	c659aebe4b	add latency of last instruction in CP	2021-11-04 11:58:40 +01:00
JanLJL	f801950ffb	better output formatting	2021-11-04 11:55:48 +01:00
Jan	2995f1873d	Merge pull request #60 from RRZE-HPC/a72 ... Add support for ARM Cortex-A72	2021-10-14 18:10:36 +02:00
JanLJL	c36fab40cb	added Cortex A72 in README	2021-10-14 17:10:08 +02:00