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6d814d416be659c8e3a2140624fd534846961e11
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402 Commits

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Author SHA1 Message Date
JanLJL
6d814d416b added docstrings 2019-11-06 17:37:35 +01:00
JanLJL
f8ed85b7c9 removed port checking for old structure and minor bugfix 2019-11-06 12:50:00 +01:00
JanLJL
db6e40ee88 removed "uopsinfo" as possible import flag since model_importer creates full DB file 2019-11-06 12:35:50 +01:00
JanLJL
8359aa4807 added new instructions/uarchs 2019-11-06 12:30:20 +01:00
JanLJL
697c5b5f4b minor updates 2019-11-06 10:54:31 +01:00
JanLJL
f3f91536b5 added missing data ports in DB and nicer CP view for frontend 2019-10-31 19:40:20 +01:00
JanLJL
687693d2a5 improved port model scheme 2019-10-31 18:47:50 +01:00
JanLJL
eb55693871 added IVB DB 2019-10-31 18:19:23 +01:00
JanLJL
abf4fc391f Merge branch 'master' of github.com:RRZE-HPC/osaca 2019-10-30 18:16:26 +01:00
JanLJL
4da262a902 better GAS suffix handling and BDW DB 2019-10-30 18:16:14 +01:00
Julian Hammer
a91413c270 added list processing function 2019-10-30 09:31:01 +01:00
Jan
6c56a77967 Update README.rst 2019-10-29 17:26:36 +01:00
JanLJL
224e24d5e9 updates 2019-10-29 17:23:33 +01:00
JanLJL
0b78d290ec enhanced by optimal throughput analysis 2019-10-29 16:52:34 +01:00
JanLJL
a839af76c5 fixed bug in load port utilization 2019-10-29 16:51:58 +01:00
JanLJL
15da6044dd bugfix in imports 2019-10-29 09:15:54 +01:00
JanLJL
0f5d3a0370 separated SemanticsAppender into ISA and Arch semantics 2019-10-29 09:09:52 +01:00
Julian Hammer
1c8067545d collapsed x86 and arm functions into generic function 2019-10-25 16:09:02 +02:00
Julian Hammer
484d6da85e made tests a module 2019-10-25 14:49:21 +02:00
Julian Hammer
0ecc656055 added marker definition to marker_utils 2019-10-25 13:16:24 +02:00
Jan
af0c8fc953 Merge pull request #45 from RRZE-HPC/v3 
ibench & asmbench interfaces
 2019-10-24 14:45:12 +02:00
JanLJL
5fe983f4ef added asmbench import 2019-10-24 14:42:21 +02:00
JanLJL
8b4acf0508 fixed last problems with ibench import 2019-10-24 12:38:26 +02:00
Julian Hammer
0c63d4f1cd added functions for extraction of basic blocks and loop bodies 2019-10-23 14:45:12 +02:00
Julian Hammer
b1e4cb90a7 better formatting of load_throughput dump 2019-10-22 14:43:43 +02:00
JanLJL
159a1fa343 added combined view for TP/CP/LDC 2019-10-16 19:00:24 +02:00
JanLJL
db862441b0 Resolved merge conflicts 2019-10-16 10:59:03 +02:00
Jan
de5479a06c Merge pull request #43 from RRZE-HPC/non_average_port_model 
Non average port model
 2019-10-16 10:39:02 +02:00
JanLJL
d92523e133 changed DBs to new port_pressure structure 2019-10-16 10:06:47 +02:00
Julian Hammer
cb7cec20a8 working importer, better dumper 2019-10-15 12:22:49 +02:00
Julian Hammer
1c673382b4 work in progress 2019-10-14 17:08:40 +02:00
Julian Hammer
85dd53dc4e versin bump 0.3.1.dev1 v0.3.1.dev1 2019-10-11 17:50:05 +02:00
Julian Hammer
792bbb1166 removed some unnecessary file checks and fixed up test cases 2019-10-11 16:13:58 +02:00
Julian Hammer
f08fbf79ba renamed semanticsAppender module, merged find_file functions 2019-10-11 15:34:24 +02:00
Julian Hammer
e7ea5451f1 fixed KerncraftAPI 2019-10-11 13:35:04 +02:00
Julian Hammer
0ed113116c returning output as string for kerncraft 2019-10-11 13:28:20 +02:00
Julian Hammer
65100bd9da made KerncraftAPI stateful 2019-10-11 13:21:33 +02:00
Julian Hammer
2995287377 directives may also have register parameters 2019-10-11 13:09:12 +02:00
Julian Hammer
209ce2a5ef better error message on parsing errors 2019-10-11 12:36:13 +02:00
Jan
3a6fa0475f bugfix 2019-10-11 09:50:14 +02:00
Jan
e2abac3e0c fixed wrond LCD test 2019-10-11 09:47:06 +02:00
JanLJL
cd81271b54 fixed testing 2019-10-10 17:59:11 +02:00
JanLJL
361a4fd8c2 moved db_interface and integrated ibench in it 2019-10-10 17:00:27 +02:00
JanLJL
c8c8c13ed1 more instructions 2019-10-10 16:36:07 +02:00
Jan
a3ba078e76 Update README.rst 2019-10-10 09:47:03 +02:00
JanLJL
438a4b3d6b small updates 2019-10-10 09:37:52 +02:00
Julian Hammer
8c2dfb27e5 enabled pypi tag deployment from travis 2019-10-09 13:36:03 +02:00
Julian
14abed8f85 Merge pull request #39 from aaronjohnson/patch-1 
Update README.rst
 2019-10-07 09:21:26 +02:00
JanLJL
39cfd4dcda ibench benchmark file creation 2019-10-04 12:21:19 +02:00
Jan
97025b259a Add files via upload 2019-10-04 10:55:24 +02:00