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876 Commits 2 Branches 44 Tags
d1201ace11e37035dd457f21929ccfbeae66a783
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71 Commits

Author SHA1 Message Date
JanLJL
d1201ace11 added more dependency analysis for post/pre indexing and condition flags 2023-03-14 17:00:02 +01:00
Décio Luiz Gazzoni Filho
19c47db3ed Support for flags and conditional ops on AArch64 2023-02-19 22:08:42 -03:00
JanLJL
7724ce27c7 added Zen3 support 2022-09-27 18:39:14 +02:00
JanLJL
ddff8c5012 added option of explicitly mentioning k regs in DB (not simply gpr) 2022-09-07 10:33:16 +02:00
JanLJL
671f7f5591 added ICX architecture 2022-08-29 11:14:56 +02:00
JanLJL
93c0753db3 formatting 2022-04-07 12:17:08 +02:00
JanLJL
d2a4749c39 added lane comparison for AArch64 reg operands 2022-01-26 14:24:48 +01:00
Qingcai Jiang
7194e79beb simple implement for TSV110 2021-11-06 16:04:16 +08:00
JanLJL
9c16f8bc56 formatted 2021-10-14 10:59:55 +02:00
JanLJL
5735291d27 Merge branch 'master' into a72 2021-10-14 10:37:05 +02:00
JanLJL
5205cb5cc6 fixed formatting with correct line length 2021-10-04 15:00:17 +02:00
JanLJL
e6ce870ca0 black formatting 2021-10-04 14:33:28 +02:00
JanLJL
d418c16f4a applied flake8 and black rules 2021-08-26 16:58:19 +02:00
Julian
08440ed5e1 Validation (#71) 
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.

build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.

For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz

The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb

Quite a few changes on OSACA included:

Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
 2021-04-15 14:42:37 +02:00
JanLJL
b0e35316f0 changed consideration of masking for database back to NO 2021-03-25 11:50:17 +01:00
Julian Hammer
6204c90934 migrate code style to Black 2021-03-11 12:02:45 +01:00
Julian Hammer
1ebe5ecfbd sanity check validity of operand entries 2021-03-11 11:38:25 +01:00
JanLJL
9a13e5cbc5 guarantee 0 latency for None values in DB 2021-03-11 01:55:57 +01:00
Git out :V
12044e3ac4 Initial support for the Cortex-A72 (Raspberry Pi 4) 2020-12-16 18:49:16 +01:00
JanLJL
23623ca18a enhancements for lookup and parsing AArch64 instrs 2020-12-07 01:18:32 +01:00
JanLJL
596a323dfb bugfixes 2020-11-21 21:00:58 +01:00
Julian Hammer
314ff4cf9d improved performance of arch_semantics and reg dependency matching 2020-11-09 19:27:47 +01:00
Julian Hammer
f64253b2b9 added dict for instruction lookup 2020-11-09 17:00:46 +01:00
JanLJL
207c53aaad minor bugfix in HW model and added user warnings for more insight 2020-11-06 15:06:36 +01:00
Julian Hammer
6b0adb5d68 improved cache handing (always hashing original file) 2020-11-06 12:27:34 +01:00
JanLJL
f9f382a948 bugfixes 2020-11-06 12:03:54 +01:00
Julian Hammer
decec86e56 fixed py3.5 compatability 2020-10-29 10:59:00 +01:00
JanLJL
9af689b28c fixed bug in tests and removed unused imports 2020-10-28 19:29:48 +01:00
Julian Hammer
9d2ea8603f new caching structure with support for distribution 2020-10-28 16:29:55 +01:00
JanLJL
e8b78e4cc6 Merge branch 'master' into A64FX 2020-10-15 22:44:12 +02:00
Julian Hammer
748474cd81 added more cmp versions 2020-10-15 16:23:14 +02:00
JanLJL
93060eee43 Merge branch 'master' into A64FX 2020-07-13 14:41:49 +02:00
Cloud User
34e978d2ae initial implementation of Neoverse N1 support 2020-06-30 20:28:57 +00:00
JanLJL
6294e2e9da initial commit for trying to support a64fx 2020-06-26 05:20:40 +02:00
Julian Hammer
9624e6c109 closing cache file after dump 2020-03-24 15:20:49 +01:00
Julian Hammer
c5801cfe2f closing cache file 2020-03-21 17:18:04 +01:00
JanLJL
1aa710f195 enhanced MachineModel to support mask/zeroing differentiation for instruction forms 2020-03-17 12:55:37 +01:00
JanLJL
17e7f0e0d8 more instruction forms and added wildcard support for registers in ISA DB 2020-03-12 15:07:51 +01:00
JanLJL
4e73e24b99 added documentation 2020-03-09 16:35:06 +01:00
Julian Hammer
0adde7b9fc added ice lake abbreviation 2020-02-05 10:05:57 +01:00
JanLJL
421cf55af7 minor enhancements and bugfixes 2020-01-27 16:37:28 +01:00
JanLJL
02233f627e added file caching for DBs 2020-01-22 15:07:46 +01:00
Julian Hammer
b2bb2cd003 small changes 2020-01-17 15:04:08 +01:00
JanLJL
c2d8742ac0 allows aliasing in uarch DB via list-name 2020-01-17 12:21:46 +01:00
JanLJL
5b1c984552 adjusted test due to hidden operand dependencies 2020-01-17 08:13:15 +01:00
JanLJL
cb100d118f small bugfix for mm registers 2020-01-14 18:24:00 +01:00
JanLJL
b6572720af enhanced for dynamic ST throughput combination 2020-01-14 10:49:47 +01:00
JanLJL
623c4ea113 added wildcard mode for mem addressing in ISA DB 2020-01-10 12:55:44 +01:00
JanLJL
bad230fa7b enhanced dynamic combine of LD and arithmetic instr 2019-12-19 18:50:48 +01:00
JanLJL
b2b4aba0f3 added default load tp in new HW model 2019-12-18 16:58:34 +01:00