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Author	SHA1	Message	Date
JanLJL	d3e5a48f47	more instruction forms	2022-09-07 12:48:39 +02:00
JanLJL	3250d87647	removed invalid char	2022-09-07 10:48:45 +02:00
JanLJL	f2338a67c6	more instruction forms	2022-09-07 10:33:28 +02:00
JanLJL	8a3255daf0	added option of explicitly mentioning k regs in DB (not simply gpr)	2022-09-07 10:33:16 +02:00
JanLJL	16cae13925	added more instructions for ICX	2022-09-01 15:49:28 +02:00
JanLJL	74ce449680	Merge branch 'master' of github.com:RRZE-HPC/osaca	2022-08-31 14:20:07 +02:00
JanLJL	6c4d5b5eef	added AND instr	2022-08-31 14:19:23 +02:00
JanLJL	f8a3d42314	fix bug in port util	2022-08-31 14:17:52 +02:00
JanLJL	484b70eb51	version bump	2022-08-29 12:03:47 +02:00
JanLJL	3336d0fe1c	added py310 in actions	2022-08-29 11:45:41 +02:00
JanLJL	b45813b696	added py310 in actions	2022-08-29 11:45:13 +02:00
JanLJL	b83c0bba8b	formatting	2022-08-29 11:30:46 +02:00
JanLJL	686fa90007	added ICX architecture	2022-08-29 11:14:56 +02:00
JanLJL	1d847f4510	black formatting	2022-06-22 17:12:53 +02:00
JanLJL	e4df8893dd	fixed #88	2022-06-22 17:09:24 +02:00
JanLJL	04b74327ef	version bump	2022-04-08 13:51:08 +02:00
JanLJL	dafaf600c7	a few more instructions	2022-04-08 12:02:05 +02:00
Jan	0b33d12711	Merge pull request #87 from RRZE-HPC/patch-linter ... Patch linter	2022-04-07 13:23:49 +02:00
JanLJL	da1879210f	removed solo black run	2022-04-07 12:18:57 +02:00
JanLJL	9bbb289f9d	formatting	2022-04-07 12:17:08 +02:00
Jan	cd3690f6f9	Update lint.yml	2022-04-07 12:12:33 +02:00
JanLJL	4b6212dc8c	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2022-04-07 10:39:16 +02:00
JanLJL	9e541dea5e	updates	2022-04-07 10:39:12 +02:00
JanLJL	7df61ba65c	removed temp file	2022-04-06 16:28:02 +02:00
Jan	b6b64edbc4	Merge pull request #84 from qcjiang/feature/tsv110 ... Feature/tsv110	2022-04-06 16:25:39 +02:00
JanLJL	6e2c58ed78	bugfixes and additions	2022-03-28 10:06:51 +02:00
Qingcai Jiang	728bb03a93	fix a bug about orr in tsv110	2022-03-20 14:53:34 +08:00
JanLJL	54da7568d9	small bugfixes	2022-03-17 16:38:28 +01:00
Qingcai Jiang	a56c972fa3	Merge branch 'feature/tsv110' of github.com:qcjiang/OSACA into feature/tsv110	2022-02-27 17:19:28 +08:00
Qingcai Jiang	d51d84afcc	adjust sshll instruction	2022-02-27 17:19:15 +08:00
Qingcai Jiang	4729e24ee9	Merge branch 'pr84' into feature/tsv110	2022-02-18 16:04:55 +08:00
Qingcai Jiang	0dbd1ab48c	Merge branch 'master' into feature/tsv110	2022-02-18 16:03:25 +08:00
Jan	86b62ecb6d	fixed typo	2022-02-14 10:42:01 +01:00
Jan	633e54af90	Merge branch 'master' into feature/tsv110	2022-01-27 10:52:39 +01:00
JanLJL	babb5e1d84	formatting	2022-01-27 10:12:00 +01:00
Jan	681278ba13	Merge pull request #85 from qcjiang/bug_fix/when_mov_is_the_last_instr ... a) fix a bug when 'mov' is the last instruction and no markers are given b) fix bug when kernel consists of only unknown load instructions	2022-01-27 10:09:28 +01:00
JanLJL	c9d63f7d3c	adjusted DB	2022-01-26 14:25:01 +01:00
JanLJL	4aeb031240	added lane comparison for AArch64 reg operands	2022-01-26 14:24:48 +01:00
Qingcai Jiang	0e04963ace	modify some instructions for tsv110	2022-01-06 16:25:08 +08:00
Qingcai Jiang	f8c23ce43d	add some instructions for tsv110	2022-01-04 20:59:35 +08:00
Qingcai Jiang	5d36b56e07	add some instructions for tsv110	2022-01-04 18:45:32 +08:00
Qingcai Jiang	81fe9be3c4	Merge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 21:33:42 +08:00
Qingcai Jiang	871a8da414	fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64	2021-12-30 21:32:29 +08:00
Qingcai Jiang	4e5b768780	fix some instr for tsv110	2021-12-30 21:24:41 +08:00
Qingcai Jiang	8a899185c2	XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 20:32:34 +08:00
Qingcai Jiang	d1450517b3	fix a bug when 'mov' is the last instruction	2021-12-30 20:30:43 +08:00
Qingcai Jiang	e20fb21679	add some instructions for tsv110, now support most of the instructions	2021-12-19 18:13:32 +08:00
QCJiang	114114e553	Merge branch 'RRZE-HPC:master' into feature/tsv110	2021-12-18 17:52:54 +08:00
Qingcai Jiang	dc2d605d6a	add some instructions for tsv110	2021-12-18 17:51:41 +08:00
Qingcai Jiang	45b70e0961	add some instructions for tsv110	2021-12-18 15:44:07 +08:00