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dev/risc-v
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77 Commits

Author SHA1 Message Date
Metehan Dundar
480c0dcac0 Merge branch 'master' into dev/risc-v 2025-05-08 12:23:22 +02:00
Metehan Dundar
aa3753d024 Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files 2025-05-08 11:57:06 +02:00
pleroy
939089030b Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write. 2025-03-27 22:47:32 +01:00
Robin Leroy
d2b8b7771f ucomisd is like comisd 2025-03-27 22:46:48 +01:00
pleroy
ea59056f94 Define comisd sources. 2025-03-27 22:46:38 +01:00
Metehan Dundar
d782f06e84 Add RISC-V support and update version to 0.6.2 2025-03-21 17:16:39 +01:00
Robin Leroy
122f8a674b Configure the dependencies of the jmeow instructions on flags 2025-03-20 22:30:00 +01:00
Robin Leroy
94f32c51a7 Add the setmeow instructions 2025-03-20 22:29:51 +01:00
Metehan Dundar
850f7edc6b RISCV.yml file has been updated. 2025-03-13 09:54:06 +01:00
Metehan Dundar
653c27135d Add initial support for RISC-V architecture and update relevant files 2025-03-11 05:10:03 +01:00
stefandesouza
686c769397 Reverted comment 2024-02-22 13:47:47 +01:00
stefandesouza
b8e88f9319 Merge remote-tracking branch 'origin/master' into InstrucForm 2023-12-16 12:14:36 +01:00
JanLJL
b7ff0b1461 bugfixes for SP reg and ccodes 2023-12-12 18:32:43 +01:00
stefandesouza
37ca6670c7 pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also 2023-12-02 16:56:43 +01:00
stefandesouza
cce05e44cb Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class 2023-10-29 13:52:49 +01:00
JanLJL
97756faa04 Merge branch 'master' into pr-armcc 2023-03-14 17:50:48 +01:00
JanLJL
1b261912e0 renamed condition code attrib, fixed incorrect src/dst, and added more conditional instructions 2023-03-14 16:57:34 +01:00
JanLJL
37c8598b36 resolve #81 2023-03-02 15:50:13 +01:00
Décio Luiz Gazzoni Filho
b434e30ec1 Support for flags and conditional ops on AArch64 2023-02-19 22:08:42 -03:00
JanLJL
16cae13925 added more instructions for ICX 2022-09-01 15:49:28 +02:00
JanLJL
686fa90007 added ICX architecture 2022-08-29 11:14:56 +02:00
Jan
b6b64edbc4 Merge pull request #84 from qcjiang/feature/tsv110 
Feature/tsv110
 2022-04-06 16:25:39 +02:00
JanLJL
6e2c58ed78 bugfixes and additions 2022-03-28 10:06:51 +02:00
JanLJL
54da7568d9 small bugfixes 2022-03-17 16:38:28 +01:00
JanLJL
d84a6399dd Closes #78, closes #79; added unary/binary logical operators 2021-11-04 12:09:44 +01:00
JanLJL
f1f119f5a0 added instructions for BHIVE 2021-09-29 17:26:44 +02:00
JanLJL
2d17a48604 updated a few DB entries 2021-06-02 16:37:18 +02:00
Julian
04836cf3f9 Validation (#71) 
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.

build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.

For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz

The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb

Quite a few changes on OSACA included:

Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
 2021-04-15 14:42:37 +02:00
Julian Hammer
5990cdc2b4 added missing instructions to all DBs 2021-04-05 16:47:52 +02:00
JanLJL
a4066633fe new instructions 2020-12-09 11:52:10 +01:00
JanLJL
3754d69e36 new instructions 2020-12-07 01:18:32 +01:00
JanLJL
15d5440259 removed false entries 2020-11-21 21:02:44 +01:00
Julian
e159fc938f Merge pull request #51 from RRZE-HPC/A64FX 
A64FX support and several Arm bugfixes and enhancements including better TP scheduling
 2020-10-16 10:44:47 +02:00
JanLJL
3cfc673e1f removed duplicate cmp entry 2020-10-16 10:11:51 +02:00
JanLJL
633e93ee4b Merge branch 'master' into A64FX 2020-10-15 22:44:12 +02:00
Julian Hammer
277d7e281e Merge branch 'master' into fix/increment_handling 2020-10-15 16:36:29 +02:00
Julian Hammer
56abb82087 added more cmp versions 2020-10-15 16:23:14 +02:00
Julian Hammer
6397605136 Merge branch 'master' into fix/increment_handling 2020-10-15 13:17:02 +02:00
Julian Hammer
3e7ebc0e01 added CMP to aarch64 to exclude first op from destinations 2020-10-15 13:15:54 +02:00
Julian Hammer
f0c84c3aee treating post- and pre-incremeted memory references no longer as src_dst 
the incremented register is now considered src_dst instead
 2020-10-13 19:25:29 +02:00
Julian Hammer
a9f497f579 fixed push and added pop 2020-10-12 15:03:03 +02:00
JanLJL
6059e3c51b Merge branch 'master' of github.com:RRZE-HPC/osaca 2020-09-17 22:15:20 +02:00
JanLJL
555e4fa1cb added instructions 2020-09-17 22:14:14 +02:00
JanLJL
1d8415c925 version bump 2020-08-03 09:38:50 +02:00
JanLJL
3b0fe8bad8 Merge branch 'master' into A64FX 2020-07-13 14:41:49 +02:00
JanLJL
33f6eaf241 bugfixes for A64FX 2020-07-06 18:48:54 +02:00
JanLJL
9694d6843d prettified aarch64 ISA DB 2020-06-25 21:54:52 +02:00
JanLJL
2b573b2cdd more instructions 2020-05-04 18:50:58 +02:00
JanLJL
c28911c060 more instructions 2020-03-30 18:27:33 +02:00
JanLJL
08923d4141 more instruction forms and added wildcard support for registers in ISA DB 2020-03-12 15:07:51 +01:00