255 Commits

Author	SHA1	Message	Date
JanLJL	5c21e18e36	more instructions	2022-10-11 15:43:19 +02:00
JanLJL	8807e3eda6	added few instrucitons	2022-10-07 00:51:09 +02:00
JanLJL	7c907e2432	bugfix in store throughput calculation	2022-09-28 14:21:46 +02:00
JanLJL	2fa25e3099	formatting for flake8	2022-09-28 10:05:18 +02:00
JanLJL	0b440e4da9	updated and bugfixed DB	2022-09-28 10:01:26 +02:00
JanLJL	08e6a4be36	updated DB	2022-09-28 10:01:14 +02:00
JanLJL	7724ce27c7	added Zen3 support	2022-09-27 18:39:14 +02:00
JanLJL	4f8e37d9fd	bugfixes and more features	2022-09-27 18:04:59 +02:00
JanLJL	d5f1654aa8	bugfixes	2022-09-27 18:04:33 +02:00
JanLJL	df747b8c48	more instruction forms	2022-09-07 12:48:39 +02:00
JanLJL	4e25a29a8a	removed invalid char	2022-09-07 10:48:45 +02:00
JanLJL	016061f72c	more instruction forms	2022-09-07 10:33:28 +02:00
JanLJL	2306cb58d0	added more instructions for ICX	2022-09-01 15:49:28 +02:00
JanLJL	660a9d0f41	Merge branch 'master' of github.com:RRZE-HPC/osaca	2022-08-31 14:20:07 +02:00
JanLJL	3b453de617	added AND instr	2022-08-31 14:19:23 +02:00
JanLJL	b93d911bb7	fix bug in port util	2022-08-31 14:17:52 +02:00
JanLJL	76542782c8	formatting	2022-08-29 11:30:46 +02:00
JanLJL	671f7f5591	added ICX architecture	2022-08-29 11:14:56 +02:00
JanLJL	a018f80597	version bump	2022-04-08 13:51:08 +02:00
JanLJL	2bc6ba999f	a few more instructions	2022-04-08 12:02:05 +02:00
JanLJL	ca0540563d	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2022-04-07 10:39:16 +02:00
JanLJL	467f212fa3	updates	2022-04-07 10:39:12 +02:00
JanLJL	0de00e512b	removed temp file	2022-04-06 16:28:02 +02:00
Jan	3d26d6b82a	Merge pull request #84 from qcjiang/feature/tsv110 ... Feature/tsv110	2022-04-06 16:25:39 +02:00
JanLJL	75bc03bc76	bugfixes and additions	2022-03-28 10:06:51 +02:00
Qingcai Jiang	fa06b9ccac	fix a bug about orr in tsv110	2022-03-20 14:53:34 +08:00
JanLJL	9c966c2359	small bugfixes	2022-03-17 16:38:28 +01:00
Qingcai Jiang	13ec7dc20e	Merge branch 'feature/tsv110' of github.com:qcjiang/OSACA into feature/tsv110	2022-02-27 17:19:28 +08:00
Qingcai Jiang	b2a326070f	adjust sshll instruction	2022-02-27 17:19:15 +08:00
Jan	0119f97942	fixed typo	2022-02-14 10:42:01 +01:00
JanLJL	a447e289ff	adjusted DB	2022-01-26 14:25:01 +01:00
Qingcai Jiang	c917a83974	modify some instructions for tsv110	2022-01-06 16:25:08 +08:00
Qingcai Jiang	5ebd8a019e	add some instructions for tsv110	2022-01-04 20:59:35 +08:00
Qingcai Jiang	fe42870cc2	add some instructions for tsv110	2022-01-04 18:45:32 +08:00
Qingcai Jiang	b484179e02	fix some instr for tsv110	2021-12-30 21:24:41 +08:00
Qingcai Jiang	c1fa5e3bce	add some instructions for tsv110, now support most of the instructions	2021-12-19 18:13:32 +08:00
Qingcai Jiang	feda03408f	add some instructions for tsv110	2021-12-18 17:51:41 +08:00
Qingcai Jiang	a738d82533	add some instructions for tsv110	2021-12-18 15:44:07 +08:00
Qingcai Jiang	4e10491fcb	add some instructions for tsv110	2021-12-15 21:51:59 +08:00
Qingcai Jiang	ca3ca56a01	add some instructions in tsv110.yml	2021-12-07 18:27:42 +08:00
Qingcai Jiang	2c530654dd	double check with every data in instructions	2021-12-07 16:58:30 +08:00
Qingcai Jiang	ce83727eaf	formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers	2021-12-07 16:33:22 +08:00
Qingcai Jiang	62746dfc9c	fix latency in str/ldr instructions	2021-12-07 16:17:00 +08:00
Qingcai Jiang	c35c16e007	fix typos	2021-12-02 22:55:39 +08:00
Qingcai Jiang	d3f081f282	add latency and TP information through ibench	2021-12-01 11:42:36 +08:00
JanLJL	f7579e83a9	added branch instructions and data for ADD	2021-11-29 18:48:13 +01:00
JanLJL	ea0576e8ce	changed data for register renaming	2021-11-29 18:39:37 +01:00
JanLJL	37cc10edde	unfified STP and LDP instructions	2021-11-29 18:34:39 +01:00
JanLJL	939abe2518	unified LOAD instructions	2021-11-29 17:48:16 +01:00
JanLJL	e120d9229b	unified STORE instructions	2021-11-29 17:32:51 +01:00