31 Commits

Author	SHA1	Message	Date
stefandesouza	2c32ccf37a	pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also	2023-12-02 16:56:43 +01:00
JanLJL	2a43676097	added p-indexing latency values for Arm architectures	2023-03-24 17:05:45 +01:00
JanLJL	a018f80597	version bump	2022-04-08 13:51:08 +02:00
JanLJL	2bc6ba999f	a few more instructions	2022-04-08 12:02:05 +02:00
Qingcai Jiang	fa06b9ccac	fix a bug about orr in tsv110	2022-03-20 14:53:34 +08:00
Qingcai Jiang	13ec7dc20e	Merge branch 'feature/tsv110' of github.com:qcjiang/OSACA into feature/tsv110	2022-02-27 17:19:28 +08:00
Qingcai Jiang	b2a326070f	adjust sshll instruction	2022-02-27 17:19:15 +08:00
Jan	0119f97942	fixed typo	2022-02-14 10:42:01 +01:00
JanLJL	a447e289ff	adjusted DB	2022-01-26 14:25:01 +01:00
Qingcai Jiang	c917a83974	modify some instructions for tsv110	2022-01-06 16:25:08 +08:00
Qingcai Jiang	5ebd8a019e	add some instructions for tsv110	2022-01-04 20:59:35 +08:00
Qingcai Jiang	fe42870cc2	add some instructions for tsv110	2022-01-04 18:45:32 +08:00
Qingcai Jiang	b484179e02	fix some instr for tsv110	2021-12-30 21:24:41 +08:00
Qingcai Jiang	c1fa5e3bce	add some instructions for tsv110, now support most of the instructions	2021-12-19 18:13:32 +08:00
Qingcai Jiang	feda03408f	add some instructions for tsv110	2021-12-18 17:51:41 +08:00
Qingcai Jiang	a738d82533	add some instructions for tsv110	2021-12-18 15:44:07 +08:00
Qingcai Jiang	4e10491fcb	add some instructions for tsv110	2021-12-15 21:51:59 +08:00
Qingcai Jiang	ca3ca56a01	add some instructions in tsv110.yml	2021-12-07 18:27:42 +08:00
Qingcai Jiang	2c530654dd	double check with every data in instructions	2021-12-07 16:58:30 +08:00
Qingcai Jiang	ce83727eaf	formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers	2021-12-07 16:33:22 +08:00
Qingcai Jiang	62746dfc9c	fix latency in str/ldr instructions	2021-12-07 16:17:00 +08:00
Qingcai Jiang	c35c16e007	fix typos	2021-12-02 22:55:39 +08:00
Qingcai Jiang	d3f081f282	add latency and TP information through ibench	2021-12-01 11:42:36 +08:00
JanLJL	f7579e83a9	added branch instructions and data for ADD	2021-11-29 18:48:13 +01:00
JanLJL	ea0576e8ce	changed data for register renaming	2021-11-29 18:39:37 +01:00
JanLJL	37cc10edde	unfified STP and LDP instructions	2021-11-29 18:34:39 +01:00
JanLJL	939abe2518	unified LOAD instructions	2021-11-29 17:48:16 +01:00
JanLJL	e120d9229b	unified STORE instructions	2021-11-29 17:32:51 +01:00
JanLJL	12095979db	adjusted non-instruction_form fields	2021-11-29 15:17:38 +01:00
Qingcai Jiang	ca5e9c3cae	add some instructions with ibench	2021-11-17 17:49:05 +08:00
Qingcai Jiang	7194e79beb	simple implement for TSV110	2021-11-06 16:04:16 +08:00