162 Commits

Author	SHA1	Message	Date
JanLJL	7930e4d704	take +- operator of offset/index in mem-addr into account	2025-03-14 18:46:12 +01:00
pleroy	d61330404b	Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. ... I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.	2025-03-12 22:26:38 +01:00
JanLJL	2cf2bf5cec	Merge branch 'master' into merge-branch	2025-03-07 14:45:44 +01:00
JanLJL	4e3994fec1	added support for <Xd>! registers and [<Xd>]! mem addresses in Arm	2025-03-07 11:49:14 +01:00
JanLJL	9c2f559983	black formatting	2025-03-05 10:20:47 +01:00
JanLJL	02716e7b41	flake8 formatting	2025-03-05 10:19:10 +01:00
JanLJL	253b0ee9d5	remove dependency on MachineModel	2025-03-04 17:44:27 +01:00
JanLJL	e37f9f119d	add default syntax for get_parser for compatibility with kerncraft	2025-03-04 17:44:02 +01:00
JanLJL	400be352e1	remove dependency on MachineModel	2025-03-04 17:42:52 +01:00
pleroy	1a7c1588f6	Add support for the Intel syntax supported by MSVC and ICC	2025-02-02 14:02:16 +01:00
JanLJL	a8cab3170c	fix #109	2024-10-01 12:00:47 +02:00
JanLJL	2d8bb99d9f	formatting	2024-08-19 15:50:37 +02:00
JanLJL	2bdc765df2	fixed bug in read-out of default store TP	2024-08-19 14:37:20 +02:00
Markus Büttner	0e69fa1e26	Update parsing of memory segments ... This addresses issue discussed in RRZE-HPC/OSACA#107. Now it can parse instructions of the form %fs:var@RELOC %fs:var@RELOC+4 %fs:var@RELOC(%rdi)	2024-07-30 16:02:16 +02:00
JanLJL	aca5511d6a	Black formatting	2024-05-02 17:04:56 +02:00
JanLJL	c9e38631d1	Flake8 formatting	2024-05-02 17:00:12 +02:00
stefandesouza	78309574ac	added prefetch operand	2024-03-18 22:29:39 +01:00
stefandesouza	4fd59eb0d0	Black formatting	2024-03-05 12:14:05 +01:00
stefandesouza	5f9de2c41d	Dump now converts classes to dicts	2024-03-05 00:18:45 +01:00
stefandesouza	38781ecc94	Port pressure returned in tuple with Memory Operand	2024-03-04 20:00:43 +01:00
stefandesouza	46004add41	Immediate operand attribute name changes	2024-02-28 13:01:37 +01:00
stefandesouza	d858827a47	Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples	2024-02-24 21:03:15 +01:00
stefandesouza	dcfe36b850	Took out name attribute from operand parent class	2024-02-24 15:46:04 +01:00
stefandesouza	7ad3438af5	Removed comments from operands	2024-02-24 14:15:25 +01:00
stefandesouza	fa95293cb0	Flags into operand class	2024-02-24 12:11:52 +01:00
stefandesouza	c2bd484170	Register attributes name change	2024-02-22 13:53:14 +01:00
stefandesouza	66e51630af	Memory attributes name change	2024-02-22 13:51:48 +01:00
stefandesouza	d4a6a9b44f	Instruction form text change	2024-02-22 13:49:56 +01:00
stefandesouza	04388af5dd	Made all attributes lower case	2024-02-22 13:48:56 +01:00
stefandesouza	1fb015b312	Formatting before PR	2024-01-10 13:05:27 +01:00
stefandesouza	226bc8eee0	Added shift and shift_op to Register Operand	2024-01-04 14:34:36 +01:00
stefandesouza	0b3508abf8	Small cleaup commit	2023-12-16 16:00:37 +01:00
stefandesouza	4647615c5c	Merge remote-tracking branch 'origin/master' into InstrucForm	2023-12-16 12:14:36 +01:00
JanLJL	c5ef5f7432	bugfixes for SP reg and ccodes	2023-12-12 18:32:43 +01:00
stefandesouza	339b06bd7f	Linters update	2023-12-10 18:25:00 +01:00
stefandesouza	8a6ae8c701	Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes	2023-12-10 17:26:43 +01:00
stefandesouza	cac4a0ebf2	flake8 standards	2023-12-03 21:04:58 +01:00
stefandesouza	cef7f8098d	Black formatting	2023-12-03 17:22:11 +01:00
stefandesouza	93ae586745	Fixed semantic and marker tests. Now only dump needs to be adjusted	2023-12-03 16:49:33 +01:00
stefandesouza	2c32ccf37a	pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also	2023-12-02 16:56:43 +01:00
stefandesouza	ebb973493b	Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working	2023-10-29 16:36:00 +01:00
stefandesouza	14a2aa0b52	Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class	2023-10-29 13:52:49 +01:00
stefandesouza	4186edbc03	added a couple of attributes	2023-10-23 21:57:01 +02:00
stefandesouza	e95278d2a2	Included 'source' and 'destination' attributes when loading isa data	2023-10-16 15:48:47 +02:00
stefandesouza	0b2753a78d	Throughput assignment adjustments	2023-09-25 23:20:10 +02:00
stefandesouza	42f96753c1	Black formatting	2023-09-12 12:45:28 +02:00
stefandesouza	a8e5a6ad46	Converting operand types read in from YAML files	2023-09-12 00:23:59 +02:00
stefandesouza	7f4f87d192	Changes for operand matching, instruction loading	2023-09-11 18:23:57 +02:00
stefandesouza	615ef82f04	Changes to accomodate the new OO style	2023-08-28 15:19:46 +02:00
stefandesouza	36549dd679	Updated list/range register resolver & applied black formatting	2023-08-26 14:51:04 +02:00