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Author SHA1 Message Date
Qingcai Jiang
e70229aa32 Merge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110 2021-12-30 21:33:42 +08:00
Qingcai Jiang
71b9a17ab8 fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64 2021-12-30 21:32:29 +08:00
Qingcai Jiang
b484179e02 fix some instr for tsv110 2021-12-30 21:24:41 +08:00
Qingcai Jiang
203ea2dfb0 XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110 2021-12-30 20:32:34 +08:00
Qingcai Jiang
0e984f4ec7 fix a bug when 'mov' is the last instruction 2021-12-30 20:30:43 +08:00
Qingcai Jiang
c1fa5e3bce add some instructions for tsv110, now support most of the instructions 2021-12-19 18:13:32 +08:00
QCJiang
0ab6efa9cb Merge branch 'RRZE-HPC:master' into feature/tsv110 2021-12-18 17:52:54 +08:00
Qingcai Jiang
feda03408f add some instructions for tsv110 2021-12-18 17:51:41 +08:00
Qingcai Jiang
a738d82533 add some instructions for tsv110 2021-12-18 15:44:07 +08:00
Qingcai Jiang
4e10491fcb add some instructions for tsv110 2021-12-15 21:51:59 +08:00
Qingcai Jiang
a87c077654 Merge branch 'bug_fix/negative_hex_address' into feature/tsv110 2021-12-15 20:04:59 +08:00
Qingcai Jiang
ca3ca56a01 add some instructions in tsv110.yml 2021-12-07 18:27:42 +08:00
Qingcai Jiang
2c530654dd double check with every data in instructions 2021-12-07 16:58:30 +08:00
Qingcai Jiang
ce83727eaf formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers 2021-12-07 16:33:22 +08:00
Qingcai Jiang
62746dfc9c fix latency in str/ldr instructions 2021-12-07 16:17:00 +08:00
Jan
ebadaba3ca Merge pull request #82 from qcjiang/bug_fix/negative_hex_address 
fix a bug when the hex_number of address is negative
 2021-12-03 14:39:04 +01:00
Jan
2be8606e9a black-conform formatting 2021-12-03 14:38:52 +01:00
Qingcai Jiang
d170ba72dd fix a bug when the hex_number of address is negative 2021-12-03 15:13:54 +08:00
Qingcai Jiang
c35c16e007 fix typos 2021-12-02 22:55:39 +08:00
Qingcai Jiang
d3f081f282 add latency and TP information through ibench 2021-12-01 11:42:36 +08:00
JanLJL
f7579e83a9 added branch instructions and data for ADD 2021-11-29 18:48:13 +01:00
JanLJL
ea0576e8ce changed data for register renaming 2021-11-29 18:39:37 +01:00
JanLJL
37cc10edde unfified STP and LDP instructions 2021-11-29 18:34:39 +01:00
JanLJL
939abe2518 unified LOAD instructions 2021-11-29 17:48:16 +01:00
JanLJL
e120d9229b unified STORE instructions 2021-11-29 17:32:51 +01:00
JanLJL
12095979db adjusted non-instruction_form fields 2021-11-29 15:17:38 +01:00
Qingcai Jiang
ca5e9c3cae add some instructions with ibench 2021-11-17 17:49:05 +08:00
Qingcai Jiang
7194e79beb simple implement for TSV110 2021-11-06 16:04:16 +08:00
JanLJL
c97f93c39b version bump v0.4.7 2021-11-04 14:56:23 +01:00
JanLJL
968c71b7b6 black formatting 2021-11-04 12:11:15 +01:00
JanLJL
df26edd075 Merge branch 'master' of github.com:RRZE-HPC/OSACA 2021-11-04 12:09:57 +01:00
JanLJL
a767b7f290 Closes #78, closes #79; added unary/binary logical operators 2021-11-04 12:09:44 +01:00
JanLJL
ba45038ad7 add latency of last instruction in CP 2021-11-04 11:58:40 +01:00
JanLJL
72e85075c2 better output formatting 2021-11-04 11:55:48 +01:00
Jan
40839384ec Merge pull request #60 from RRZE-HPC/a72 
Add support for ARM Cortex-A72
 2021-10-14 18:10:36 +02:00
JanLJL
ab615547e5 added Cortex A72 in README 2021-10-14 17:10:08 +02:00
JanLJL
9c16f8bc56 formatted 2021-10-14 10:59:55 +02:00
JanLJL
be891d45d4 formatted 2021-10-14 10:53:34 +02:00
JanLJL
5735291d27 Merge branch 'master' into a72 2021-10-14 10:37:05 +02:00
JanLJL
ab368cded1 unified format 2021-10-14 09:23:35 +02:00
JanLJL
6e99954f0b version bump v0.4.6 2021-10-07 17:10:17 +02:00
JanLJL
5205cb5cc6 fixed formatting with correct line length 2021-10-04 15:00:17 +02:00
JanLJL
e6ce870ca0 black formatting 2021-10-04 14:33:28 +02:00
JanLJL
566fbc6bc4 black conformity 2021-09-30 15:53:56 +02:00
JanLJL
b70cff21ad added instructions for BHIVE 2021-09-29 17:26:44 +02:00
JanLJL
d181184788 enhanced parser 2021-09-29 17:26:27 +02:00
Jan
fcc3475417 added lint configs 2021-08-27 08:14:50 +02:00
JanLJL
d418c16f4a applied flake8 and black rules 2021-08-26 16:58:19 +02:00
JanLJL
34523e1b23 fixed wrong uops info import with masking of some gather/scatter 2021-08-26 11:05:33 +02:00
JanLJL
457ccdcf77 version bump v0.4.5 2021-07-21 02:41:05 +02:00