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Author	SHA1	Message	Date
Qingcai Jiang	fa06b9ccac	fix a bug about orr in tsv110	2022-03-20 14:53:34 +08:00
JanLJL	9c966c2359	small bugfixes	2022-03-17 16:38:28 +01:00
Qingcai Jiang	13ec7dc20e	Merge branch 'feature/tsv110' of github.com:qcjiang/OSACA into feature/tsv110	2022-02-27 17:19:28 +08:00
Qingcai Jiang	b2a326070f	adjust sshll instruction	2022-02-27 17:19:15 +08:00
Qingcai Jiang	2eb6023b7a	Merge branch 'pr84' into feature/tsv110	2022-02-18 16:04:55 +08:00
Qingcai Jiang	c2787babee	Merge branch 'master' into feature/tsv110	2022-02-18 16:03:25 +08:00
Jan	0119f97942	fixed typo	2022-02-14 10:42:01 +01:00
Jan	6514257767	Merge branch 'master' into feature/tsv110	2022-01-27 10:52:39 +01:00
JanLJL	e1a5272fdf	formatting	2022-01-27 10:12:00 +01:00
Jan	5748b2987b	Merge pull request #85 from qcjiang/bug_fix/when_mov_is_the_last_instr ... a) fix a bug when 'mov' is the last instruction and no markers are given b) fix bug when kernel consists of only unknown load instructions	2022-01-27 10:09:28 +01:00
JanLJL	a447e289ff	adjusted DB	2022-01-26 14:25:01 +01:00
JanLJL	d2a4749c39	added lane comparison for AArch64 reg operands	2022-01-26 14:24:48 +01:00
Qingcai Jiang	c917a83974	modify some instructions for tsv110	2022-01-06 16:25:08 +08:00
Qingcai Jiang	5ebd8a019e	add some instructions for tsv110	2022-01-04 20:59:35 +08:00
Qingcai Jiang	fe42870cc2	add some instructions for tsv110	2022-01-04 18:45:32 +08:00
Qingcai Jiang	e70229aa32	Merge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 21:33:42 +08:00
Qingcai Jiang	71b9a17ab8	fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64	2021-12-30 21:32:29 +08:00
Qingcai Jiang	b484179e02	fix some instr for tsv110	2021-12-30 21:24:41 +08:00
Qingcai Jiang	203ea2dfb0	XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110	2021-12-30 20:32:34 +08:00
Qingcai Jiang	0e984f4ec7	fix a bug when 'mov' is the last instruction	2021-12-30 20:30:43 +08:00
Qingcai Jiang	c1fa5e3bce	add some instructions for tsv110, now support most of the instructions	2021-12-19 18:13:32 +08:00
QCJiang	0ab6efa9cb	Merge branch 'RRZE-HPC:master' into feature/tsv110	2021-12-18 17:52:54 +08:00
Qingcai Jiang	feda03408f	add some instructions for tsv110	2021-12-18 17:51:41 +08:00
Qingcai Jiang	a738d82533	add some instructions for tsv110	2021-12-18 15:44:07 +08:00
Qingcai Jiang	4e10491fcb	add some instructions for tsv110	2021-12-15 21:51:59 +08:00
Qingcai Jiang	a87c077654	Merge branch 'bug_fix/negative_hex_address' into feature/tsv110	2021-12-15 20:04:59 +08:00
Qingcai Jiang	ca3ca56a01	add some instructions in tsv110.yml	2021-12-07 18:27:42 +08:00
Qingcai Jiang	2c530654dd	double check with every data in instructions	2021-12-07 16:58:30 +08:00
Qingcai Jiang	ce83727eaf	formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers	2021-12-07 16:33:22 +08:00
Qingcai Jiang	62746dfc9c	fix latency in str/ldr instructions	2021-12-07 16:17:00 +08:00
Jan	ebadaba3ca	Merge pull request #82 from qcjiang/bug_fix/negative_hex_address ... fix a bug when the hex_number of address is negative	2021-12-03 14:39:04 +01:00
Jan	2be8606e9a	black-conform formatting	2021-12-03 14:38:52 +01:00
Qingcai Jiang	d170ba72dd	fix a bug when the hex_number of address is negative	2021-12-03 15:13:54 +08:00
Qingcai Jiang	c35c16e007	fix typos	2021-12-02 22:55:39 +08:00
Qingcai Jiang	d3f081f282	add latency and TP information through ibench	2021-12-01 11:42:36 +08:00
JanLJL	f7579e83a9	added branch instructions and data for ADD	2021-11-29 18:48:13 +01:00
JanLJL	ea0576e8ce	changed data for register renaming	2021-11-29 18:39:37 +01:00
JanLJL	37cc10edde	unfified STP and LDP instructions	2021-11-29 18:34:39 +01:00
JanLJL	939abe2518	unified LOAD instructions	2021-11-29 17:48:16 +01:00
JanLJL	e120d9229b	unified STORE instructions	2021-11-29 17:32:51 +01:00
JanLJL	12095979db	adjusted non-instruction_form fields	2021-11-29 15:17:38 +01:00
Qingcai Jiang	ca5e9c3cae	add some instructions with ibench	2021-11-17 17:49:05 +08:00
Qingcai Jiang	7194e79beb	simple implement for TSV110	2021-11-06 16:04:16 +08:00
JanLJL	c97f93c39b	version bump v0.4.7	2021-11-04 14:56:23 +01:00
JanLJL	968c71b7b6	black formatting	2021-11-04 12:11:15 +01:00
JanLJL	df26edd075	Merge branch 'master' of github.com:RRZE-HPC/OSACA	2021-11-04 12:09:57 +01:00
JanLJL	a767b7f290	Closes #78, closes #79; added unary/binary logical operators	2021-11-04 12:09:44 +01:00
JanLJL	ba45038ad7	add latency of last instruction in CP	2021-11-04 11:58:40 +01:00
JanLJL	72e85075c2	better output formatting	2021-11-04 11:55:48 +01:00
Jan	40839384ec	Merge pull request #60 from RRZE-HPC/a72 ... Add support for ARM Cortex-A72	2021-10-14 18:10:36 +02:00