Commit Graph

Select branches

Hide Pull Requests

dev/risc-v

master

#1

#101

#102

#105

#108

#112

#114

#115

#116

#117

#12

#14

#17

#18

#27

#39

#4

#43

#44

#45

#48

#49

#5

#50

#51

#58

#59

#60

#62

#65

#71

#8

#80

#82

#83

#84

#85

#86

#87

#92

#95

#96

0.4.11

v0.2.1

v0.2.2

v0.3.1

v0.3.1.dev1

v0.3.10

v0.3.11

v0.3.12

v0.3.13

v0.3.14

v0.3.2

v0.3.2.dev1

v0.3.2.dev2

v0.3.2.dev3

v0.3.2.dev4

v0.3.2.dev5

v0.3.3.dev0

v0.3.4

v0.3.6

v0.3.7

v0.3.8

v0.3.9

v0.4.0

v0.4.1

v0.4.10

v0.4.11

v0.4.12

v0.4.13

v0.4.2

v0.4.3

v0.4.4

v0.4.5

v0.4.6

v0.4.7

v0.4.8

v0.4.9

v0.5.0

v0.5.1

v0.5.2

v0.5.3

v0.6.0

v0.6.1

v0.7.0

v0.7.1

Mono Color

• 871a8da414 fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64 Qingcai Jiang 2021-12-30 21:32:29 +08:00
• 71b9a17ab8 fix a bug when longest_path is not integer, try 'ldpw3, w1, [x0, #0x48]' in AArch64 Qingcai Jiang 2021-12-30 21:32:29 +08:00
• 4e5b768780 fix some instr for tsv110 Qingcai Jiang 2021-12-30 21:24:41 +08:00
• b484179e02 fix some instr for tsv110 Qingcai Jiang 2021-12-30 21:24:41 +08:00
• 8a899185c2 XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110 Qingcai Jiang 2021-12-30 20:32:34 +08:00
• 203ea2dfb0 XMerge branch 'bug_fix/when_mov_is_the_last_instr' into feature/tsv110 Qingcai Jiang 2021-12-30 20:32:34 +08:00
• d1450517b3 fix a bug when 'mov' is the last instruction Qingcai Jiang 2021-12-30 20:30:43 +08:00
• 0e984f4ec7 fix a bug when 'mov' is the last instruction Qingcai Jiang 2021-12-30 20:30:43 +08:00
• e20fb21679 add some instructions for tsv110, now support most of the instructions Qingcai Jiang 2021-12-19 18:13:32 +08:00
• c1fa5e3bce add some instructions for tsv110, now support most of the instructions Qingcai Jiang 2021-12-19 18:13:32 +08:00
• 114114e553 Merge branch 'RRZE-HPC:master' into feature/tsv110 QCJiang 2021-12-18 17:52:54 +08:00
• 0ab6efa9cb Merge branch 'RRZE-HPC:master' into feature/tsv110 QCJiang 2021-12-18 17:52:54 +08:00
• dc2d605d6a add some instructions for tsv110 Qingcai Jiang 2021-12-18 17:51:41 +08:00
• feda03408f add some instructions for tsv110 Qingcai Jiang 2021-12-18 17:51:41 +08:00
• 45b70e0961 add some instructions for tsv110 Qingcai Jiang 2021-12-18 15:44:07 +08:00
• a738d82533 add some instructions for tsv110 Qingcai Jiang 2021-12-18 15:44:07 +08:00
• b9c4f228b7 add some instructions for tsv110 Qingcai Jiang 2021-12-15 21:51:59 +08:00
• 4e10491fcb add some instructions for tsv110 Qingcai Jiang 2021-12-15 21:51:59 +08:00
• b1f3b150fa Merge branch 'bug_fix/negative_hex_address' into feature/tsv110 Qingcai Jiang 2021-12-15 20:04:59 +08:00
• a87c077654 Merge branch 'bug_fix/negative_hex_address' into feature/tsv110 Qingcai Jiang 2021-12-15 20:04:59 +08:00
• 871b79af90 add some instructions in tsv110.yml Qingcai Jiang 2021-12-07 18:27:42 +08:00
• ca3ca56a01 add some instructions in tsv110.yml Qingcai Jiang 2021-12-07 18:27:42 +08:00
• 3860253601 double check with every data in instructions Qingcai Jiang 2021-12-07 16:58:30 +08:00
• 2c530654dd double check with every data in instructions Qingcai Jiang 2021-12-07 16:58:30 +08:00
• 3b0dfc7141 formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers Qingcai Jiang 2021-12-07 16:33:22 +08:00
• ce83727eaf formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers Qingcai Jiang 2021-12-07 16:33:22 +08:00
• a89e31350e fix latency in str/ldr instructions Qingcai Jiang 2021-12-07 16:17:00 +08:00
• 62746dfc9c fix latency in str/ldr instructions Qingcai Jiang 2021-12-07 16:17:00 +08:00
• 70fd12a360 Merge pull request #82 from qcjiang/bug_fix/negative_hex_address Jan 2021-12-03 14:39:04 +01:00
• ebadaba3ca Merge pull request #82 from qcjiang/bug_fix/negative_hex_address Jan 2021-12-03 14:39:04 +01:00
• b18f7bf718 black-conform formatting Jan 2021-12-03 14:38:52 +01:00
• 2be8606e9a black-conform formatting Jan 2021-12-03 14:38:52 +01:00
• 3efda4ba6c fix a bug when the hex_number of address is negative Qingcai Jiang 2021-12-03 15:09:38 +08:00
• d170ba72dd fix a bug when the hex_number of address is negative Qingcai Jiang 2021-12-03 15:09:38 +08:00
• 2059269d8a fix typos Qingcai Jiang 2021-12-02 22:55:39 +08:00
• c35c16e007 fix typos Qingcai Jiang 2021-12-02 22:55:39 +08:00
• be48dd6c1b add latency and TP information through ibench Qingcai Jiang 2021-12-01 11:42:36 +08:00
• d3f081f282 add latency and TP information through ibench Qingcai Jiang 2021-12-01 11:42:36 +08:00
• fb2dbfa83f added branch instructions and data for ADD JanLJL 2021-11-29 18:48:13 +01:00
• f7579e83a9 added branch instructions and data for ADD JanLJL 2021-11-29 18:48:13 +01:00
• b43f4374b1 changed data for register renaming JanLJL 2021-11-29 18:39:37 +01:00
• ea0576e8ce changed data for register renaming JanLJL 2021-11-29 18:39:37 +01:00
• a111ce7e89 unfified STP and LDP instructions JanLJL 2021-11-29 18:34:39 +01:00
• 37cc10edde unfified STP and LDP instructions JanLJL 2021-11-29 18:34:39 +01:00
• fd628a0dde unified LOAD instructions JanLJL 2021-11-29 17:48:16 +01:00
• 939abe2518 unified LOAD instructions JanLJL 2021-11-29 17:48:16 +01:00
• a8a6f42061 unified STORE instructions JanLJL 2021-11-29 17:32:51 +01:00
• e120d9229b unified STORE instructions JanLJL 2021-11-29 17:32:51 +01:00
• 1359cc92ba adjusted non-instruction_form fields JanLJL 2021-11-29 15:17:38 +01:00
• 12095979db adjusted non-instruction_form fields JanLJL 2021-11-29 15:17:38 +01:00
• de0982226b add some instructions with ibench Qingcai Jiang 2021-11-17 17:49:05 +08:00
• ca5e9c3cae add some instructions with ibench Qingcai Jiang 2021-11-17 17:49:05 +08:00
• 2d38cac9a1 simple implement for TSV110 Qingcai Jiang 2021-11-06 16:04:16 +08:00
• 7194e79beb simple implement for TSV110 Qingcai Jiang 2021-11-06 16:04:16 +08:00
• 6f3b36e58c version bump JanLJL 2021-11-04 14:56:23 +01:00
• c97f93c39b version bump v0.4.7 JanLJL 2021-11-04 14:56:23 +01:00
• f901b481da black formatting JanLJL 2021-11-04 12:11:15 +01:00
• 968c71b7b6 black formatting JanLJL 2021-11-04 12:11:15 +01:00
• 1d6e0d5a42 Merge branch 'master' of github.com:RRZE-HPC/OSACA JanLJL 2021-11-04 12:09:57 +01:00
• df26edd075 Merge branch 'master' of github.com:RRZE-HPC/OSACA JanLJL 2021-11-04 12:09:57 +01:00
• d84a6399dd Closes #78, closes #79; added unary/binary logical operators JanLJL 2021-11-04 12:09:44 +01:00
• a767b7f290 Closes #78, closes #79; added unary/binary logical operators JanLJL 2021-11-04 12:09:44 +01:00
• c659aebe4b add latency of last instruction in CP JanLJL 2021-11-04 11:58:40 +01:00
• ba45038ad7 add latency of last instruction in CP JanLJL 2021-11-04 11:58:40 +01:00
• f801950ffb better output formatting JanLJL 2021-11-04 11:55:48 +01:00
• 72e85075c2 better output formatting JanLJL 2021-11-04 11:55:48 +01:00
• 2995f1873d Merge pull request #60 from RRZE-HPC/a72 Jan 2021-10-14 18:10:36 +02:00
• 40839384ec Merge pull request #60 from RRZE-HPC/a72 Jan 2021-10-14 18:10:36 +02:00
• c36fab40cb added Cortex A72 in README JanLJL 2021-10-14 17:10:08 +02:00
• ab615547e5 added Cortex A72 in README JanLJL 2021-10-14 17:10:08 +02:00
• 4e967380d6 formatted JanLJL 2021-10-14 10:59:55 +02:00
• 9c16f8bc56 formatted JanLJL 2021-10-14 10:59:55 +02:00
• 3789e065c6 formatted JanLJL 2021-10-14 10:53:34 +02:00
• be891d45d4 formatted JanLJL 2021-10-14 10:53:34 +02:00
• 3971e9e853 Merge branch 'master' into a72 JanLJL 2021-10-14 10:37:05 +02:00
• 5735291d27 Merge branch 'master' into a72 JanLJL 2021-10-14 10:37:05 +02:00
• 3b20246fc3 unified format JanLJL 2021-10-14 09:23:35 +02:00
• ab368cded1 unified format JanLJL 2021-10-14 09:23:35 +02:00
• 8c94378437 version bump JanLJL 2021-10-07 17:10:17 +02:00
• 6e99954f0b version bump v0.4.6 JanLJL 2021-10-07 17:10:17 +02:00
• bc7761007c fixed formatting with correct line length JanLJL 2021-10-04 15:00:17 +02:00
• 5205cb5cc6 fixed formatting with correct line length JanLJL 2021-10-04 15:00:17 +02:00
• 314feb4104 black formatting JanLJL 2021-10-04 14:33:28 +02:00
• e6ce870ca0 black formatting JanLJL 2021-10-04 14:33:28 +02:00
• 217fcff664 black conformity JanLJL 2021-09-30 15:53:56 +02:00
• 566fbc6bc4 black conformity JanLJL 2021-09-30 15:53:56 +02:00
• f1f119f5a0 added instructions for BHIVE JanLJL 2021-09-29 17:26:44 +02:00
• b70cff21ad added instructions for BHIVE JanLJL 2021-09-29 17:26:44 +02:00
• 3404d72dc5 enhanced parser JanLJL 2021-09-29 17:26:27 +02:00
• d181184788 enhanced parser JanLJL 2021-09-29 17:26:27 +02:00
• b2e914db4a added lint configs Jan 2021-08-27 08:14:50 +02:00
• fcc3475417 added lint configs Jan 2021-08-27 08:14:50 +02:00
• 1b40c10a1f applied flake8 and black rules JanLJL 2021-08-26 16:58:19 +02:00
• d418c16f4a applied flake8 and black rules JanLJL 2021-08-26 16:58:19 +02:00
• db30a4e36c fixed wrong uops info import with masking of some gather/scatter JanLJL 2021-08-26 11:05:33 +02:00
• 34523e1b23 fixed wrong uops info import with masking of some gather/scatter JanLJL 2021-08-26 11:05:33 +02:00
• 44f3c0376e version bump JanLJL 2021-07-21 02:41:05 +02:00
• 457ccdcf77 version bump v0.4.5 JanLJL 2021-07-21 02:41:05 +02:00
• a721d0941d added more load instrs JanLJL 2021-07-21 02:34:31 +02:00
• ff61c65d58 added more load instrs JanLJL 2021-07-21 02:34:31 +02:00